Low Capacitance TVS Diode Array
For High-Speed Data Interfaces
PROTECTION PRODUCTS
Description
The LCDA series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to
ESD and other voltage-induced transient events. Each
device will protect two high-speed lines. They are
available with operating voltages of 5V, 12V, 15V and
24V. They are bidirectional devices and may be used on
lines where the signal polarities are above and below
ground.
TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable charac-
teristics for board level protection including fast re-
sponse time, low operating and clamping voltage and
no device degradation. The LCDA series devices
feature low capacitance compensation diodes in series
with standard TVS diodes to provide an integrated, low
capacitance solution for use on high-speed interfaces.
The LCDA series devices may be used to meet the
immunity requirements of IEC 61000-4-2, level 4.
LCDA05 THRU LCDA24
Features
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Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
IEC 61000-4-5 (Lightning) 24A (tp = 8/20µs)
Protects two I/O lines
Low capacitance for high-speed data lines
Working voltages: 5V, 12V, 15V and 24V
Low leakage current
Low operating and clamping voltages
Solid-state silicon avalanche technology
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Mechanical Characteristics
JEDEC SO-8 (MS-012AA) small outline package
Molding compound flammability rating: UL 94V-0
Marking : Part Number, Logo, Date Code
Packaging : Tape and Reel per EIA 481
Applications
High-Speed Data Lines
Microprocessor Based Equipment
Universal Serial Bus (USB) Port Protection
Notebooks, Desktops, & Servers
Instrumentation
LAN/WAN Equipment
Peripherals
Circuit Diagram (Each Line Pair)
Schematic & PIN Configuration
1
8
2
7
3
6
4
5
SO-8 (Top View)
Revision 9/2000
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Pow er (tp = 8/20µs)
Lead Soldering Temp erature
Op erating Temp erature
Storage Temp erature
Symbo l
P
p k
T
L
T
J
T
STG
Value
300
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
°C
°C
°C
Electrical Characteristics
LCDA05
Par ame te r
Reverse Stand -Off Voltage
Reverse Breakd ow n Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbo l
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 1A , tp = 8/20µ s
I
PP
= 5A , tp = 8/20µ s
Betw een I/O Pins and
Gnd
V
R
= 0V, f = 1MHz
6
20
9.8
11
5
Co nd itio ns
Minimum
Typ ical
Maximum
5
Units
V
V
µA
V
V
pF
LCDA12
Par ame te r
Reverse Stand -Off Voltage
Reverse Breakd ow n Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbo l
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
PP
= 1A , tp = 8/20µ s
I
PP
= 5A , tp = 8/20µ s
Betw een I/O Pins and
Gnd
V
R
= 0V, f = 1MHz
13.3
1
19
24
5
Co nd itio ns
Minimum
Typ ical
Maximum
12
Units
V
V
µA
V
V
pF
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Electrical Characteristics
(continued)
LCDA15
Par ame te r
Reverse Stand-Off Voltage
Reverse Breakdow n Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbo l
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 15V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
Betw een I/O Pins and
Gnd
V
R
= 0V, f = 1MHz
16.7
1
24
30
5
Co nd itio ns
Minimum
Typ ical
Maximum
15
Units
V
V
µA
V
V
pF
LCDA24
Par ame te r
Reverse Stand-Off Voltage
Reverse Breakdow n Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbo l
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 24V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
Betw een I/O Pins and
Gnd
V
R
= 0V, f = 1MHz
26.7
1
43
55
5
Co nd itio ns
Minimum
Typ ical
Maximum
24
Units
V
V
µA
V
V
pF
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
100
Peak Pulse Power - P
PP
(kW)
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
0
25
50
75
100
o
Power Derating Curve
1
0.1
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Waveform
Parameters:
tr = 8µs
td = 20µs
ESD Pulse Waveform (Per IEC 61000-4-2)
ESD Discharge Parameters Per IEC 61000-4-2
Level
First
Peak
Current
(A)
7.5
15
22.5
30
Peak
Current
at 30ns
(A)
4
8
12
16
Peak
Current
at 60ns
(A)
8
4
6
8
Test
Test
Voltage
Voltage
(Contact
( A ir
Discharge) Discharge)
(kV)
(kV)
2
4
6
8
2
4
8
15
1
2
3
4
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Applications Information
Device Connection for Protection of Two High-Speed
Data Lines
The LCDAxx is designed to protect up to two high-speed
data lines. The LCDAxx utilizes a low capacitance
compensation diode in series with, but in opposite
polarity to a TVS diode in each line. The resulting
capacitance is less than 5pF per line. Each line will
only suppress transient events in one polarity. There-
fore, to achieve protection in both positive and nega-
tive polarity, a second TVS/rectifier pair is connected in
anti-parallel to the first. Pins 1, 2, 7, and 8 are used to
protect one data line. Pins 3, 4, 5, and 6 are used to
protect the second data line.
The device is connected as follows:
l
I/O 1
2
7
LCDA Connection Diagram
1
8
I/O 1
3
I/O 2
4
6
I/O 2
5
I/O Line Protection
Pins 1 & 2 are tied together and pins 7 & 8 are tied
together providing the protection circuit for one I/O
line. Pins 3 & 4 are tied together and pins 5 & 6
are tied together providing the protection circuit for
the second I/O line. Since the device is electrically
symmetrical, either side of the connected pairs
may be used to protect the lines. The other side of
the pair is used to make the ground connection.
The ground connections should be made directly to
the ground plane for best results. The path length
is kept as short as possible to reduce the effects
of parasitic inductance in the board traces.
Connection Options
To Protected
Device
1
8
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
l
l
l
l
l
l
Line 1
In/Out
2
7
Line 1
Ground
3
6
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Line 2
Ground
4
5
Line 2
In/Out
From Connector
To Protected
Device
Line 1
In/Out
1
8
2
7
Ground
3
6
4
Line 2
In/Out
5
From Connector
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