K4J55323QG
256M GDDR3 SDRAM
256Mbit GDDR3 SDRAM
Revision 1.1
November 2005
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Revision History
Revision
0.0
0.1
Month
February
March
Year
2005
2005
-
Target Spec
History
256M GDDR3 SDRAM
- Changed EMRS table for Driver Impedance control.
- Typo corrected.
- Added clock frequency change sequence on page 18 and IBIS spec on page 19~21
- Reduced Cin min. value on page 54.
- Added note for RFM pin on page 4.
- Modified input functional description for CK/CK and Vref on page 5.
- Removed -BC10/11 from the spec. Accordingly, CL12~15 become "reserved" in MRS table.
- Modified note description for RMF on page 4.
- Modified input functional description for Mirror function on page 5.
- Modified note description for the Write Latency on page 55.
- Clarify RMF description on page 4,5 to avoid confusion in case of using same board for both
512Mb and 256Mb GDDR3.
- Added note description for Boundary scan function on page 22,23.
(one RFM ball in the scan oder will be read as a logic "0")
- Typo corrected.
- Finalized DC characteristics and IBIS specification
- Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543
0.2
March
2005
0.3
April
2005
0.4
May
2005
1.0
1.1
June
November
2005
2005
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K4J55323QG
256M GDDR3 SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
1.0 FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.8V + 0.1V power supply for device operation
1.8V + 0.1V power supply for I/O interface
On-Die Termination (ODT)
Output Driver Strength adjustment by EMRS
Calibrated output drive
1.8V Pseudo Open drain compatible inputs/outputs
4 internal banks for concurrent operation
Differential clock inputs (CK and CK)
Commands entered on each positive CK edge
CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
Additive latency (AL): 0 and 1 (clock)
Programmable Burst length : 4 and 8
Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
Single ended READ strobe (RDQS) per byte
•
•
•
•
•
•
•
•
•
•
•
•
•
Single ended WRITE strobe (WDQS) per byte
RDQS edge-aligned with data for READs
WDQS center-aligned with data for WRITEs
Data Mask(DM) for masking WRITE data
Auto & Self refresh modes
Auto Precharge option
32ms, auto refresh (4K cycle)
136 Ball FBGA
Maximum clock frequency up to 800MHz
Maximum data rate up to 1.6Gbps/pin
DLL for outputs
Boundary scan function with SEN pin
Mirror function with MF pin
2.0 ORDERING INFORMATION
Part Number
K4J55323QG-BC12
K4J55323QG-BC14
K4J55323QG-BC16
K4J55323QG-BC20
Max Freq.
800MHz
700MHz
600MHz
500MHz
Max Data Rate
1.6Gbps/pin
1.4Gbps/pin
1.2Gbps/pin
1.0Gbps/pin
Pseudo
Open Drain_18
136 Ball FBGA
Interface
Package
K4J55323QC-AC** is leaded package part number
3.0 GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
The K4J55323QG is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fab-
ricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
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4.0 PIN CONFIGURATION
Normal Package (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
2
VDD
DQ0
DQ2
WDQS0
DQ4
DQ6
VSSQ
A1
RFU1
A10
VSSQ
DQ24
DQ26
WDQS3
DQ28
DQ30
VDD
3
VSS
DQ1
DQ3
RDQS0
DM0
DQ5
DQ7
RAS
RFU2
A2
DQ25
DQ27
DM3
RDQS3
DQ29
DQ31
VSS
4
ZQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS
BA0
CKE
VDDQ
A0
A11
A3
VDDQ
VSSQ
VDDQ
VSSQ
SEN
5
6
7
8
9
MF
VSSQ
VDDQ
VSSQ
VDDQ
CS
BA1
WE
VDDQ
A4
A7
A9
VDDQ
VSSQ
VDDQ
VSSQ
RESET
256M GDDR3 SDRAM
10
VSS
DQ9
DQ11
RDQS1
DM1
DQ13
DQ15
RFM
CK
A6
DQ17
DQ19
DM2
RDQS2
DQ21
DQ23
VSS
11
VDD
DQ8
DQ10
WDQS1
DQ12
DQ14
VSSQ
A5
CK
A8/AP
VSSQ
DQ16
DQ18
WDQS2
DQ20
DQ22
VDD
12
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
Note :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however,
either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3)
becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either
static HIGH or floating state on this pin will not cause any problem for the DRAM
Please refer to Mirror Function Signal Mapping table at page 6.
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5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK
Type
Input
Function
256M GDDR3 SDRAM
Clock:
CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing). CK, CK should be maintained stable, except self-refresh mode
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers
and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks
idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and
for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read
and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during self refresh.
Chip Select:
All commands are masked when CS is registered HIGH. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM
pins are input only, the DM loading matches the DQ and WDQS loading.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is
being applied.
Address Inputs:
Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW)
or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The
address inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.
Data Input/ Output:
Bi-directional data bus.
READ Data Strobe:
Output with read data. RDQS is edge-aligned with read data.
WRITE Data Strobe:
Input with write data. WDQS is center-aligned to the inout data.
No Connect:
No internal electrical connection is present.
CKE
Input
CS
RAS, CAS,
WE
DM0
~DM3
BA0,BA1
Input
Input
Input
Input
A0 ~ A11
Input
DQ0
~ DQ31
RDQS0
~ RDQS3
WDQS0
~ WDQS3
NC/RFU
V
DDQ
V
SSQ
V
DD
V
SS
V
DDA
V
SSA
V
REF
MF
ZQ
RES
SEN
RFM
Input/
Output
Output
Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
DQ Power Supply
DQ Ground
Power Supply
Ground
DLL Power Supply
DLL Ground
Reference voltage:
0.7*VDDQ ,
2 Pins :
(H12) for Data input , (H1) for CMD and ADDRESS
Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input.
Reset pin: RESET pin is a VDDQ CMOS input
Scan enable :
Must tie to the ground in case not in use. VDDQ CMOS input.
Reserved for Mirror Function
:
When the MF ball is tied low, RFM(H10) is recommended to be driven to logic low state.
When the MF ball is tied high, RAS(H3) switch to RFM and is recommended to be driven to logic low state
Reference Resistor connection pin for On-die termination.
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Rev. 1.1 November 2005
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