GS820H32AT/Q-150/138/133/117/100/66
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• High Output Drive current.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or QFP package.
-150
Pipeline tCycle 6.6ns
3-1-1-1 t
KQ
3.8ns
I
DD
270mA
Flow tCycle 10.5ns
Through t
KQ
9ns
2-1-1-1 I
DD
170mA
-138
-133
-117
-100
-66
7.25ns 7.5ns 8.5ns 10ns 12.5ns
4ns
4ns
4.5
5ns
6ns
245mA 240mA 210mA 180mA 150mA
15ns 15ns 15ns 15ns 20ns
9.7ns 10ns 11ns 12ns 18ns
120mA 120mA 120mA 120mA 95mA
64K x 32
2M Synchronous Burst SRAM
Flow Through / Pipeline Reads
150Mhz - 66Mhz
9ns - 18ns
3.3V VDD
3.3V & 2.5V I/O
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
Pipelined Reads
The GS820H32A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Functional Description
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Core and Interface Voltages
The GS820H32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (V
DDQ
)
pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/O’s, chip enables (E
1
, E
2
, E
3
), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Rev: 1.04 3/2000
1/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A 100 Pin TQFP and QFP Pinout
NC
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
64K x 32
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.04 3/2000
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
2/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NC
© 2000, Giga Semiconductor, Inc.
E
GS820H32AT/Q-150/138/133/117/100/66
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
87
93, 94
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
Symbol
A
0
, A
1
A
2
-
15
DQ
A1
-DQ
A8
DQ
B1
-DQ
B8
DQ
C1
-DQ
C8
DQ
D1
-DQ
D8
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
I
I
Description
Address field LSB’s and Address Counter preset Inputs
Address Inputs
I/O
Data Input and Output pins.
No Connect
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQ
A
, DQ
B
Data I/O’s. Active Low.
Byte Write Enable for DQ
C
, DQ
D
Data I/O’s. Active Low.
Clock Input Signal. Active High.
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
Chip Enable. Active High.
Output Enable. Active Low.
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
Core power supply.
I/O and Core Ground.
Output driver power supply.
H
Rev: 1.04 3/2000
3/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A Block Diagram
Register
A0-An
D
Q
A0
D0
A1
D1
Q1
Counter
Load
A
Q0
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
D
Register
D
B
B
Q
32
4
32
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
Register
E
1
E
2
E
3
D
Q
Register
D
Q
FT
G
Power Down
Control
ZZ
DQx1-DQx8
Rev: 1.04 3/2000
4/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Pin Name State
LBO
FT
ZZ
L
H or NC
L
H or NC
L or NC
H
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
I
nterleaved Burst Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
Read
Write byte
A
Write byte
B
Write byte
C
Write byte
D
Write all bytes
Write all bytes
GW
H
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
L
X
B
A
X
H
L
H
H
H
L
X
B
B
X
H
H
L
H
H
L
X
B
C
X
H
H
H
L
H
L
X
B
D
X
H
H
H
H
L
L
X
Notes
1
1
2, 3
2, 3
2, 3, 4
2, 3, 4
2, 3, 4
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 3/2000
5/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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