74VHC00 Quad 2-Input NAND Gate
October 1992
Revised February 2005
74VHC00
Quad 2-Input NAND Gate
General Description
The VHC00 is an advanced high-speed CMOS 2-Input
NAND Gate fabricated with silicon gate CMOS technology.
It achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer output, which provide high noise
immunity and stable output. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
Features
s
High Speed: t
PD
3.7ns (typ) at T
A
V
NIL
25
q
C
28% V
CC
(min)
s
High noise immunity: V
NIH
s
Low noise: V
OLP
s
Power down protection is provided on all inputs
0.8V (max)
2
P
A (max) at T
A
25
q
C
s
Low power dissipation: I
CC
s
Pin and function compatible with 74HC00
Ordering Code:
Order Number
74VHC00M
74VHC00MX_NL
74VHC00SJ
74VHC00MTC
74VHC00MTCX_NL
(Note 1)
74VHC00N
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
A
L
L
H
H
B
L
H
L
H
O
H
H
H
L
© 2005 Fairchild Semiconductor Corporation
DS011504
www.fairchildsemi.com
74VHC00
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
20 mA
r
20 mA
r
25 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 3)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
V
CC
3.3V
r
0.3V
5.0V
r
0.5V
0 ns/V
a
100 ns/V
0 ns/V
a
20 ns/V
2.0V to
5.5V
0V to
5.5V
0V to V
CC
40
q
C to
85
q
C
Note 2:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
T
A
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
I
OL
I
OL
V
IN
V
IN
4 mA
8 mA
V
V
V
IN
or V
IL
I
OH
I
OH
V
IH
I
OL
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
1.50
0.7 V
CC
Units
V
Conditions
0.50
0.3 V
CC
V
V
IN
or V
IL
V
IH
I
OH
50
P
A
4mA
8mA
50
P
A
r
0.1
2.0
r
1.0
20.0
P
A
P
A
5.5V or GND
V
CC
or GND
Noise Characteristics
Symbol
V
OLP
(Note 4)
V
OLV
(Note 4)
V
IHD
(Note 4)
V
ILD
(Note 4)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.0
1.5
V
C
L
50 pF
5.0
3.5
V
C
L
50 pF
5.0
V
CC
(V)
5.0
T
A
Typ
0.3
25
q
C
Limit
0.8
Units
V
V
C
L
C
L
50 pF
50 pF
Conditions
0.3
0.8
Note 4:
Parameter guaranteed by design
www.fairchildsemi.com
2
Test/Measurement
京公网安备 11010802033920号
EEWORLD
