White Electronic Designs
32Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 72
Weight: W332M72V-XSBX - 2.0 grams typical
W332M72V-XSBX
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 134,217,728-bit banks is organized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
BENEFITS
73% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 23% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
* This product is subject to change without notice.
Discrete Approach
11.9
11.9
11.9
11.9
11.9
ACTUAL SIZE
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
W332M72V-XSBX
16
22
S
A
V
I
N
G
S
73%
23%
Area
I/O
Count
Ju;y 2006
Rev. 3
5 x 265mm
2
= 1325mm
2
5 x 54 pins = 270 pins
1
352mm
2
208 Balls
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 1 – PIN CONFIGURATION
Top View
W332M72V-XSBX
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CCQ
2
V
CC
3
V
SS
4
V
CCQ
5
V
CCQ
6
V
SS
7
V
CCQ
8
V
CCQ
9
V
SS
10 11
V
CC
V
SS
V
SS
CS2#
CS0#
CKE2
CKE0
CAS2#
RAS0#
RAS2#
V
SS
V
CCQ
V
SS
NC
NC
CLK0
CLK2
DQML0
DQML2
CAS0#
WE0#
WE2#
V
SS
DQMH2
DQMH0
NC
NC
DQ8
DQ40
DQ5
DQ39
DQ7
NC
NC
DQ41
DQ9
DQ10
DQ42
DQ43
DQ12
DQ3
DQ36
DQ4
DQ38
DQ6
DQ44
DQ11
DQ13
DQ45
DQ14
DQ33
DQ1
DQ34
DQ2
DQ37
DQ35
DQ64
DQ65
DQ15
DQ47
DQ46
V
SS
DQ32
DQ0
DQ77
DQ79
DQ78
DNU
DQ66
DQ69
DNU
DQ67
V
CC
DQ72
DQ73
DQ74
DQ75
DQ76
V
CCQ
A12
BA1
A0
V
CC
V
SS
V
CCQ
A7
A9
NC(A13)
V
CC
V
SS
A10
A3
V
CCQ
V
SS
NC
V
SS
V
CCQ
A4
A11
V
SS
V
CC
A2
BA0
A1
V
CCQ
V
SS
V
CC
A6
A8
A5
V
CCQ
DQ71
DQ70
NC
DQML4
DQ68
V
CC
NC
DQMH4
NC
CLK4
DNU
WE4#
CAS4#
RAS4#
DQ16
DQ48
V
SS
DQ63
DQ31
DQ62
CKE4
CS4#
DQ22
DQ52
DQ18
DQ50
DQ17
DQ49
DQ30
DQ61
DQ29
DQ59
DQ27
DQ23
DQ54
DQ21
DQ19
DQ51
DQ60
DQ28
DQ58
DQ26
DQ57
DQ25
NC
NC
DQ55
DQ53
DQ20
DQ56
DQ24
DQMH3
DQMH1
NC
NC
V
SS
CAS3#
WE3#
WE1#
DQML3
DQML1
NC
NC
CLK1
CLK3
V
SS
V
CCQ
V
SS
CAS1#
RAS3#
RAS1#
CKE1
CKE3
CS1#
CS3#
V
SS
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally
Ball J10 is NC on this device; will be used as A13 for future density upgrades.
Ju;y 2006
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE
0
#
RAS
0
#
CAS
0
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
CLK
0
CKE
0
CS
0
#
DQML
0
DQMH
0
CLK
CKE
CS#
DQML
DQMH
W332M72V-XSBX
A
0-12
BA
0-1
DQ
0
U0
DQ
15
DQ
15
WE
1
#
RAS
1
#
CAS
1
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
CLK
1
CKE
1
CS
1
#
DQML
1
DQMH
1
CLK
CKE
CS#
DQML
DQMH
DQ
16
U1
DQ
15
DQ
31
WE
2
#
RAS
2
#
CAS
2
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
CLK
2
CKE
2
CS
2
#
DQML
2
DQMH
2
CLK
CKE
CS#
DQML
DQMH
DQ
32
U2
DQ
15
DQ
47
WE
3
#
RAS
3
#
CAS
3
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
CLK
3
CKE
3
CS
3
#
DQML
3
DQMH
3
CLK
CKE
CS#
DQML
DQMH
DQ
48
U3
DQ
15
DQ
63
WE
4
#
RAS
4
#
CAS
4
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
CLK
4
CKE
4
CS
4
#
DQML
4
DQMH
4
CLK
CKE
CS#
DQML
DQMH
DQ
64
U4
DQ
15
DQ
79
Ju;y 2006
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
W332M72V-XSBX
Register Definition
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the WRITE burst mode,
and M10 and M11 are reserved for future use. Address
A12 (M12) is undefined but should be driven LOW during
loading of the mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
pro grammed number of locations in a pro grammed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-9) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-9 when the burst length is set to two; by A2-9 when
the burst length is set to four; and by A3-9 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached
Initialization
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming. Because
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
Ju;y 2006
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 3 – MODE REGISTER DEFINITION
Burst
Length
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
W332M72V-XSBX
TABLE 1 – BURST DEFINITION
Starting Column
Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
2
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
Mode Register (Mx)
Reserved*
WB Op Mode
CAS Latency
BT
Burst Length
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
2
4
8
4
Burst Length
M3 = 0
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
8
M3
0
1
Burst Type
Sequential
Interleaved
A2
0
0
0
0
1
1
1
1
M6 M5 M4
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
n = A
0-9
(location 0-y)
M8
0
-
M7
0
-
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
NOTES:
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
Ju;y 2006
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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