W332M72V-133SBC datasheet, PDF

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W332M72V-133SBC: Description32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208; Categorystorage storage; File Size473KB，15 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W332M72V-133SBC Overview

32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208

W332M72V-133SBC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	White Electronic Designs Corporation
package instruction	BGA, BGA208,11X19,40
Reach Compliance Code	unknow
access mode	FOUR BANK PAGE BURST
Maximum access time	5.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B208
memory density	2415919104 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	208
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX72
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA208,11X19,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.225 A
Maximum slew rate	0.575 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

W332M72V-133SBC Preview

White Electronic Designs

32Mx72 Synchronous DRAM

FEATURES

High Frequency = 100, 125, 133MHz

Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

3.3V ±0.3V power supply for core and I/Os

Fully Synchronous; all signals registered on positive

edge of system clock cycle

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

Organized as 32M x 72

Weight: W332M72V-XSBX - 2.0 grams typical

W332M72V-XSBX

GENERAL DESCRIPTION

The 256MByte (2Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 5 chips containing

536,870,912 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 134,217,728-bit banks is organized as 8,192

rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option. An AUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

The 2Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is compatible

with the 2n rule of prefetch architectures, but it also allows

the column address to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging

one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless, high-

speed, random-access operation.

The 2Gb SDRAM is designed to operate at 3.3V. An auto

refresh mode is provided, along with a power-saving,

power-down mode.

BENEFITS

73% SPACE SAVINGS

Reduced part count

Reduced I/O count

• 23% I/O Reduction

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

* This product is subject to change without notice.

Discrete Approach

11.9

ACTUAL SIZE

22.3

TSOP

White Electronic Designs

W332M72V-XSBX

73%

23%

Area

I/O

Count

Ju;y 2006

Rev. 3

5 x 265mm

= 1325mm

5 x 54 pins = 270 pins

352mm

208 Balls

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FIGURE 1 – PIN CONFIGURATION

Top View

W332M72V-XSBX

CCQ

10 11

CS2#

CS0#

CKE2

CKE0

CAS2#

RAS0#

RAS2#

CCQ

CLK0

CLK2

DQML0

DQML2

CAS0#

WE0#

WE2#

DQMH2

DQMH0

DQ8

DQ40

DQ5

DQ39

DQ7

DQ41

DQ9

DQ10

DQ42

DQ43

DQ12

DQ3

DQ36

DQ4

DQ38

DQ6

DQ44

DQ11

DQ13

DQ45

DQ14

DQ33

DQ1

DQ34

DQ2

DQ37

DQ35

DQ64

DQ65

DQ15

DQ47

DQ46

DQ32

DQ0

DQ77

DQ79

DQ78

DNU

DQ66

DQ69

DNU

DQ67

DQ72

DQ73

DQ74

DQ75

DQ76

CCQ

A12

BA1

CCQ

NC(A13)

A10

CCQ

A11

BA0

CCQ

DQ71

DQ70

DQML4

DQ68

DQMH4

CLK4

DNU

WE4#

CAS4#

RAS4#

DQ16

DQ48

DQ63

DQ31

DQ62

CKE4

CS4#

DQ22

DQ52

DQ18

DQ50

DQ17

DQ49

DQ30

DQ61

DQ29

DQ59

DQ27

DQ23

DQ54

DQ21

DQ19

DQ51

DQ60

DQ28

DQ58

DQ26

DQ57

DQ25

DQ55

DQ53

DQ20

DQ56

DQ24

DQMH3

DQMH1

CAS3#

WE3#

WE1#

DQML3

DQML1

CLK1

CLK3

CCQ

CAS1#

RAS3#

RAS1#

CKE1

CKE3

CS1#

CS3#

CCQ

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.

NC = Not Connected Internally

Ball J10 is NC on this device; will be used as A13 for future density upgrades.

Ju;y 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQML

DQMH

CLK

CKE

CS#

DQML

DQMH

W332M72V-XSBX

0-12

0-1

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQML

DQMH

CLK

CKE

CS#

DQML

DQMH

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQML

DQMH

CLK

CKE

CS#

DQML

DQMH

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQML

DQMH

CLK

CKE

CS#

DQML

DQMH

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CLK

CKE

DQML

DQMH

CLK

CKE

CS#

DQML

DQMH

Ju;y 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance,

including the ability to synchronously burst data at a high

data rate with automatic column-address generation,

the ability to interleave between internal banks in order

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during a

burst access.

W332M72V-XSBX

MODE REGISTER

The Mode Register is used to deﬁne the speciﬁc mode

of operation of the SDRAM. This deﬁnition includes the

selec-tion of a burst length, a burst type, a CAS latency,

an operating mode and a write burst mode, as shown in

Figure 3. The Mode Register is programmed via the LOAD

MODE REGISTER command and will retain the stored

information until it is programmed again or the device

loses power.

Mode register bits M0-M2 specify the burst length, M3

speciﬁes the type of burst (sequential or interleaved),

M4-M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9 speciﬁes the WRITE burst mode,

and M10 and M11 are reserved for future use. Address

A12 (M12) is undeﬁned but should be driven LOW during

loading of the mode register.

The Mode Register must be loaded when all banks are

idle, and the controller must wait the speciﬁed time before

initiating the subsequent operation. Violating either of these

requirements will result in unspeciﬁed operation.

FUNCTIONAL DESCRIPTION

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

pro grammed number of locations in a pro grammed

sequence. Accesses begin with the registration of an

ACTIVE command which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0 and BA1 select the bank,

A0-12 select the row). The address bits (A0-9) registered

coincident with the READ or WRITE command are used to

select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.

The following sections provide detailed information

covering device initialization, register deﬁnition, command

descriptions and device operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented,

with the burst length being programmable, as shown in

Figure 3. The burst length determines the maximum

number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 1, 2, 4

or 8 locations are available for both the sequential and the

interleaved burst types, and a full-page burst is available

for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command to

generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation

or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1-9 when the burst length is set to two; by A2-9 when

the burst length is set to four; and by A3-9 when the burst

length is set to eight. The remaining (least signiﬁcant)

address bit(s) is (are) used to select the starting location

within the block. Full-page bursts wrap within the page if

the boundary is reached

Initialization

SDRAMs must be powered up and initialized in a predeﬁned

manner. Operational procedures other than those speciﬁed

may result in undeﬁned operation. Once power is applied

to V

and V

CCQ

(simultaneously) and the clock is stable

(stable clock is deﬁned as a signal cycling within timing

constraints specified for the clock pin), the SDRAM

requires a 100µs delay prior to issuing any command

other than a COMMAND INHIBIT or a NOP. Starting at

some point during this 100µs period and continuing at

least through the end of this period, COMMAND INHIBIT

or NOP commands should be applied.

Once the 100µs delay has been satisﬁed with at least

one COMMAND INHIBIT or NOP command having been

applied, a PRECHARGE command should be applied. All

banks must be precharged, thereby placing the device in

the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be

performed. After the AUTO REFRESH cycles are complete,

the SDRAM is ready for Mode Register programming. Because

the Mode Register will power up in an unknown state, it should

be loaded prior to applying any operational command.

Ju;y 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

FIGURE 3 – MODE REGISTER DEFINITION

Burst

Length

Address Bus

W332M72V-XSBX

TABLE 1 – BURST DEFINITION

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential

0-1

1-0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1,

Cn…

Type = Interleaved

0-1

1-0

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

Not Supported

Mode Register (Mx)

Reserved*

WB Op Mode

CAS Latency

Burst Length

*Should program

M12, M11, M10 = 0, 0

to ensure compatibility

with future devices.

M2 M1M0

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

Burst Length

M3 = 0

M3 = 1

Reserved

Full Page

Burst Type

Sequential

Interleaved

M6 M5 M4

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

CAS Latency

Reserved

Full

Page

(y)

n = A

0-9

(location 0-y)

M6-M0

Defined

Operating Mode

Standard Operation

All other states reserved

Write Burst Mode

Programmed Burst Length

Single Location Access

NOTES:

1. For full-page accesses: y = 1,024.

2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting

column within the block.

3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting

column within the block.

4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the

starting column within the block.

5. For a full-page burst, the full row is selected and A0-9 select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the

following access wraps within the block.

7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode

Ju;y 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W332M72V-133SBC Related Products

	W332M72V-133SBC	W332M72V-100SBM	W332M72V-125SBM	W332M72V-133SBM	W332M72V-XSBX	W332M72V-133SBI	W332M72V-100SBI
Description	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208	32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208
memory width	72	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1
Number of terminals	208	208	208	208	208	208	208
Maximum operating temperature	70 °C	125 °C	125 °C	125 °C	125 Cel	85 °C	85 °C
Minimum operating temperature	-	-55 °C	-55 °C	-55 °C	-55 Cel	-40 °C	-40 °C
organize	32MX72	32MX72	32MX72	32MX72	32MX72	32MX72	32MX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
surface mount	YES	YES	YES	YES	YES	YES	YES
Temperature level	COMMERCIAL	MILITARY	MILITARY	MILITARY	MILITARY	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	-	incompatible	incompatible
Maker	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	-	White Electronic Designs Corporation	White Electronic Designs Corporation
package instruction	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	-	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40
Reach Compliance Code	unknow	unknow	unknow	unknow	-	unknow	unknown
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.5 ns	7 ns	6 ns	5.5 ns	-	5.5 ns	7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	100 MHz	125 MHz	133 MHz	-	133 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	-	COMMON	COMMON
JESD-30 code	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208	-	R-PBGA-B208	R-PBGA-B208
memory density	2415919104 bi	2415919104 bi	2415919104 bi	2415919104 bi	-	2415919104 bi	2415919104 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
word count	33554432 words	33554432 words	33554432 words	33554432 words	-	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	-	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	-	BGA	BGA
Encapsulate equivalent code	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40	-	BGA208,11X19,40	BGA208,11X19,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	-	8192	8192
self refresh	YES	YES	YES	YES	-	YES	YES
Maximum standby current	0.225 A	0.225 A	0.225 A	0.225 A	-	0.225 A	0.225 A
Maximum slew rate	0.575 mA	0.575 mA	0.575 mA	0.575 mA	-	0.575 mA	0.575 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	-	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V
technology	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS
Terminal pitch	1 mm	1 mm	1 mm	1 mm	-	1 mm	1 mm
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
length	-	22 mm	22 mm	-	22 mm	-	22 mm
width	-	16 mm	16 mm	-	16 mm	-	16 mm

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