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AS7C1026A

Description
5V/3.3V 64K X 16 CMOS SRAM
File Size136KB,9 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
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AS7C1026A Overview

5V/3.3V 64K X 16 CMOS SRAM

AS7C1026A Preview

January 2001
Advance Information
®
AS7C1026A
AS7C31026A
5V/3.3V 64K X 16 CMOS SRAM
Features
• AS7C1026A (5V version)
• AS7C31026A (3.3V version)
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• Low power consumption: ACTIVE
- 660 mW (AS7C1026A) / max @ 10 ns
- 324 mW (AS7C31026A) / max @ 10 ns
• ESD protection
2000 volts
• Latch-up current
200 mA
• Low power consumption: STANDBY
- 55 mW (AS7C1026A) / max CMOS I/O
- 36 mW (AS7C31026A) / max CMOS I/O
Logic block diagram
A0
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
Pin arrangement
44-Pin SOJ, TSOP II (400 mil)
V
CC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
48-CSP mini Ball-Grid-Array Package
Row decoder
A1
64K × 16
Array
GND
I/O
buffer
Control circuit
Column decoder
A8
A9
A10
A11
A12
A13
A14
A15
WE
A
B
C
D
E
F
G
H
1
LB
I/O8
I/O9
V
SS
V
DD
I/O14
I/O15
NC
2
3
OE
A
0
UB
A3
I/O10 A5
I/O11 NC
I/O12 NC
I/O13 A14
NC A12
A8
A9
4
A
1
A4
A6
A7
NC
A15
A13
A10
5
A
2
CE
I/O1
I/O3
I/O4
I/O5
WE
A11
6
NC
I/O0
I/O2
V
DD
V
SS
I/O6
I/O7
NC
UB
OE
LB
CE
Selection guide
AS7C1026A-10
AS7C31026A-10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby
current
AS7C1026A-12
AS7C31026A-12
AS7C1026A-15
AS7C31026A-15
AS7C1026A-20
AS7C31026A-20
Unit
10
3
120
90
10
10
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
12
3
110
80
10
10
15
4
100
80
10
10
20
5
100
80
15
15
ns
ns
mA
mA
mA
mA
2/6/01; V.0.9
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1026A
AS7C31026A
Functional description
The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 3/3/4/5 ns are ideal for
high-performance applications.
When CE is high the devices enter standby mode. The AS7C1026A is guaranteed not to exceed 55 mW power consumption in CMOS
standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026A) or 3.3V supply (AS7C31026A). the
device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest
possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC
applied
DC current into outputs (low)
AS7C1026A
AS7C31026A
Both
Both
Both
Both
Both
Symbol
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–0.50
–65
–55
Max
+7.0
+5.0
V
CC
+0.50
1.0
+150
+125
20
Unit
V
V
V
W
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
L
L
L
WE
X
H
H
H
L
L
L
H
X
OE
X
L
L
L
X
X
X
H
X
LB
X
L
H
L
L
L
H
X
H
UB
X
H
L
L
L
H
L
X
H
I/O0–I/O7 I/O8–I/O15
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
High Z
High Z
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
D
IN
High Z
Mode
Standby (I
SB
), I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
Write I/O8–I/O15 (I
CC
)
Output disable (I
CC
)
Key:
H = High, L = Low, X = don’t care.
2/6/01; V.0.9
Alliance Semiconductor
P. 2 of 9
®
AS7C1026A
AS7C31026A
Recommended operating conditions
Parameter
Supply voltage
Device
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
Both
commercial
industrial
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL†
T
A
T
A
Min
4.5
3.0
2.2
2.0
–0.5
0
–40
Nominal
5.0
3.3
Max
5.5
3.6
V
CC
+ 0.5
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
V
V
o
C
o
C
Input voltage
Ambient operating temperature
V
IL
min. = –3.0V for pulse width less than t
RC
/2.
DC operating characteristics (over the operating range)
1
-10
Parameter
Input leakage
current
Output leakage
current
Operating power
supply current
-12
-15
-20
Min Max Unit
1
µA
Sym
|
I
LI
|
|
I
LO
|
Test conditions
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max
CE = V
IH
,
V
OUT
= GND to V
CC
V
CC
= Max, CE
V
IL
outputs open,
f = f
Max
= 1/t
RC
V
CC
= Max, CE
V
IL
,
outputs open,
f = f
Max
= 1/t
RC
V
CC
= Max, CE
V
CC
–0.2V,
V
IN
GND + 0.2V or
V
IN
V
CC
–0.2V, f = 0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Device
Both
Min Max Min Max Min Max
1
1
1
Both
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
AS7C1026A
AS7C31026A
2.4
1
120
90
30
30
10
10
0.4
2.4
1
110
80
25
25
10
10
0.4
2.4
1
100
80
20
20
10
10
0.4
2.4
1
100
80
20
20
15
15
0.4
µA
mA
mA
mA
I
CC
Standby
power supply
current
I
SB
I
SB1
V
OL
V
OH
mA
V
V
Output
voltage
Data retention
current
I
CCDR
V
CC
= 2.0V
CE
V
CC
–0.2V
V
IN
V
CC
–0.2V or
V
IN
0.2V
1
1
1
1
1
1
5
5
mA
mA
Capacitance (f = 1MHz, T
a
= 25
°C,
V
CC
= NOMINAL)
2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE, LB, UB
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
2/6/01; V.0.9
Alliance Semiconductor
P. 3 of 9
®
AS7C1026A
AS7C31026A
Read cycle (over the operating range)
3,9
-10
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
Byte select access time
Byte select Low to low Z
Byte select High to high Z
OE High to output in high Z
Power up time
Power down time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
Min
10
2
0
0
0
0
Max
10
10
3
3
3
5
3
10
12
3
0
0
0
0
-12
Min
Max
12
12
3
3
3
6
3
12
15
3
0
0
0
0
-15
Min
Max
15
15
4
4
4
6
4
15
20
3
0
0
0
0
-20
Min
Max Unit
20
20
5
5
5
8
5
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)
3,6,7,9
t
RC
Address
Data
OUT
t
OH
Previous data valid
t
AA
Data valid
t
OH
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
t
RC
Address
t
AA
OE
t
OLZ
CE
t
LZ
LB, UB
t
BLZ
Data
IN
t
BA
Data valid
t
BHZ
t
ACE
t
OHZ
t
HZ
t
OE
t
OH
2/6/01; V.0.9
Alliance Semiconductor
P. 4 of 9
®
AS7C1026A
AS7C31026A
Write cycle (over the operating range)
11
-10
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Byte select low to end of write
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
10
8
8
0
7
0
5
0
1
8
6
-12
12
10
9
0
8
0
6
0
1
10
6
15
12
10
0
9
0
8
0
1
12
-15
6
-20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
Notes
20
12
12
0
12
0
10
0
2
12
8
Symbol Min Max Min Max Min Max Min Max
Write waveform 1 (WE controlled)
10,11
t
WC
Address
t
CW
CE
t
BW
LB, UB
t
AS
WE
t
DW
Data
IN
t
WZ
Data
OUT
Data undefined
Data valid
t
OW
high Z
t
WC
Address
t
AS
CE
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
Data
IN
t
CLZ
Data
OUT
2/6/01; V.0.9
high Z
t
WZ
Data undefined
high Z
P. 5 of 9
Data valid
t
OW
t
DH
t
WR
t
DH
t
AW
t
WP
t
WR
Write waveform 2 (CE controlled)
10,11
Alliance Semiconductor

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