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SEMICONDUCTOR
TECHNICAL DATA
MC68EC030
Technical Summary
Second-Generation 32-Bit Enhanced Embedded
Controller
The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:
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Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors
Burst-Mode Bus Interface for Efficient DRAM Access
On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)
Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices
25- and 40-MHz Operating Frequency (up to 9.2 MIPS)
Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications
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Additional features of the MC68EC030 include:
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Complete 32-Bit Nonmultiplexed Address and Data Buses
Sixteen 32-Bit General-Purpose Data and Address Registers
Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers
Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection
Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution
Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)
Complete Support for Coprocessors with the M68000 Coprocessor Interface
Internal Status Indication for Hardware Emulation Support
4-Gbyte Direct Addressing Range
Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size
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This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
©MOTOROLA INC., 1991
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Rev. 1
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INTRODUCTION
The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.
The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-
chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.
The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure
1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.
CONTROLLER
CLOCK (40 MHz)
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20 MHz
OSC.
MC88916
3
MC68EC030
(40 MHz)
BUS CLOCK
(20 MHz)
BUS CLOCK
(40 MHz)
BUS CLOCK
(80 MHz)
Figure 1.
MC68EC030 Clock Circuitry
The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing
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information. The instruction pipe and other individual control sections provide the secondary decode of
instructions and generate the actual control signals that result in the decoding and interpretation of
nanoROM and microROM information.
The instruction and data cache blocks operate independently from the rest of the machine, storing
information read by the bus controller for future use with very fast access time. Each cache resides on its
own address bus and data bus, allowing simultaneous access to both. The data and instruction caches
are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache misses.
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4
MICROSEQUENCER AND
CONTROL
INSTRUCTION PIPE
STAGE
D
INTERNAL
DATA
BUS
STAGE
C
STAGE
B
CACHE
HOLDING
REGISTER
(CAHR)
CONTROL
STORE
CONTROL
LOGIC
INSTRUCTION
CACHE
INSTRUCTION
ADDRESS
BUS
EXECUTION UNIT
ADDRESS
PROGRAM
COUNTER
SECTION
ADDRESS
SECTION
DATA
SECTION
SIZE
MULTIPLEXER
DATA
PADS
DATA
BUS
ACCESS
CONTROL
UNIT
ADDRESS
BUS
MISALIGNMENT
MULTIPLEXER
DATA
ADDRESS
BUS
BUS CONTROLLER
WRITE PENDING
BUFFER
MICROBUS
CONTROLLER
PREFETCH PENDING
BUFFER
DATA
CACHE
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BUS CONTROL
SIGNALS
ADDRESS
BUS
ADDRESS
PADS
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Figure 2. Block Diagram
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The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.
PROGRAMMING MODEL
As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general-
purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, the
address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.
31
16 15
8
7
0
D0
D1
D2
D3
D4
D5
D6
D7
31
16 15
0
A0
A1
A2
A3
A4
A5
A6
31
16 15
0
A7
(USP)
31
0
PC
15
0
8 7
0
CCR
PROGRAM
COUNTER
USER STACK
POINTER
ADDRESS
REGISTERS
DATA
REGISTERS
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CONDITION CODE
REGISTER
Figure 3. User Programming Model
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