UltraCap
®
Single cell
5000 F/ 2.5 V
Series/Type:
Ordering code:
Date:
B49410B2506Q000
March 2005
© EPCOS AG 2005. Reproduction, publication and dissemination of this data sheet, enclosures hereto and the
information contained therein without EPCOS' prior express consent is prohibited.
Purchase orders are subject to the General Conditions for the Supply of Products and Services of the Electrical
and Electronics Industry recommended by the ZVEI (German Electrical and Electronic Manufacturers' Associ-
ation), unless otherwise agreed.
UltraCap
®
Single cell, 5000 F/ 2.5 V
B49410B2506Q000
Features
Screw terminals M8
×
12
Power type
Insulated with polyurethane
Short-circuit-proof
Note
Do not put into fire!
Do not open the capacitor!
To avoid health and fire hazards, do not
operate the capacitor beyond the voltage or
temperature limits given in the data sheet.
Any excess may also result in a reduction of
lifetime.
Please pay also attention to the transport
and waste disposal instructions in chapter
"Cautions".
Dimensional drawing
Dimensions in mm
Electrical specifications
Rated capacitance
Tolerance of C
R
Rated voltage
Capacity
Specific power
Specific power
Stored energy
Specific energy
Specific energy
Surge voltage
Maximum series resistance
Maximum series resistance
Weight
Volume
Operating temperature range
Storage temperature
Lifetime (hours)
2)
Lifetime (cycles)
3)
(T
A
= 25
°C;
DCC)
1)
(T
A
= 25
°C)
(IEC 62391-2)
(IEC 62391-2)
(V = V
R
)
(V = V
R
)
(V = V
R
)
(T
A
= 25
°C;
1 kHz)
(T
A
= 25
°C;
50 mHz)
(without terminals)
(V = 0 V)
(T
A
= 25
°C;
V = V
R
)
(T
A
= 25
°C;
I = 100 A)
T
op
T
st
C
R
V
R
5000
10/+30
2.5
3500
2.0
2.3
15625
4.1
4.7
2.8
180
350
1050
0.93
30/+70
40/+70
90000
500000
F
%
V
mAh
kW/kg
kW/I
J
Wh/kg
Wh/I
V
µΩ
µΩ
g
I
°C
°C
h
cycles
E
V
surge
ESR
ESR
DC
1) DCC: discharging with constant current.
2) Requirements:
∆C/C
R
≤
30%, ESR
≤
2 times of specified limit, I
leak
≤
2 times of initial value.
3) Requirements:
∆C/C
R
≤
30%, ESR
≤
2 times of specified limit, I
leak
≤
2 times of initial value (1 cycle: charging to V
R
, 30 s rest,
discharging to V
R
/2, 30 s rest).
2
FPGA/CPLD
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