ISPLSI1032EA-125 datasheet, PDF

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ISPLSI1032EA-125: DescriptionEE PLD, 10 ns, PQFP100; Categorysemiconductor Programmable logic devices; File Size173KB，16 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPLSI1032EA-125 Overview

EE PLD, 10 ns, PQFP100

ISPLSI1032EA-125 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Rated supply voltage	5 V
Number of input and output buses	64
Processing package description	TQFP-100
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
organize	2 DEDICATED INPUTS, 64 I/O
Maximum FCLK clock frequency	77 MHz
Output function	MACROCELL
Programmable logic type	EE PLD
propagation delay TPD	10 ns
Dedicated input quantity	2

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ispLSI 1032EA

In-System Programmable High Density PLD

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 64 I/O Pins, Four Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally and Pinout Compatible with

ispLSI 1032E

• NEW FEATURES

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems (V

CCIO

Pin)

— Open-Drain Output Option

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 200 MHz Maximum Operating Frequency

—

= 4.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

D Q

Output Routing Pool

D Q

Logic

Array

D Q

GLB

D Q

Global Routing Pool (GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Description

The ispLSI 1032EA is a High Density Programmable

Logic Device containing 192 Registers, 64 Universal I/O

pins, four Dedicated Input pins, four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1032EA features 5V in-system

programmability (ISP™) and in-system diagnostic capa-

bilities via IEEE 1149.1 Test Access Port. The ispLSI

1032EA device offers non-volatile reprogrammability of

the logic, as well as the interconnects to provide truly

reconfigurable systems. A functional superset of the

ispLSI 1032 architecture, the ispLSI 1032EA device adds

user selectable 3.3V or 5V I/O and open-drain output

options.

The basic unit of logic on the ispLSI 1032EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…D7 (Figure 1). There are a total of 32 GLBs in the

ispLSI 1032EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and dedicated inputs. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com

January 2000

1032ea_02

Output Routing Pool

0139A(A1)-isp

ISPLSI1032EA-125 Related Products

	ISPLSI1032EA-125	ISPLSI1032EA	ISPLSI1032EA-100	ISPLSI1032EA-170	ISPLSI1032EA-200
Description	EE PLD, 10 ns, PQFP100	EE PLD, 10 ns, PQFP100	EE PLD, 10 ns, PQFP100	EE PLD, 10 ns, PQFP100	EE PLD, 10 ns, PQFP100
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
Maximum operating temperature	70 Cel	70 Cel	70 Cel	70 Cel	70 Cel
Minimum operating temperature	0.0 Cel	0.0 Cel	0.0 Cel	0.0 Cel	0.0 Cel
Maximum supply/operating voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply/operating voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Rated supply voltage	5 V	5 V	5 V	5 V	5 V
Number of input and output buses	64	64	64	64	64
Processing package description	TQFP-100	TQFP-100	TQFP-100	TQFP-100	TQFP-100
state	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS	CMOS	CMOS	CMOS
packaging shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes	Yes	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
organize	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O
Maximum FCLK clock frequency	77 MHz	77 MHz	77 MHz	77 MHz	77 MHz
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay TPD	10 ns	10 ns	10 ns	10 ns	10 ns
Dedicated input quantity	2	2	2	2	2

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