21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Features
•
•
•
•
•
•
•
•
•
•
•
Low On-Resistance
On-Resistance Matching Between Channels, 0.2Ω typ
On-Resistance Flatness, <2Ω typ
Low Off-Channel Leakage, <100pA @ +25oC
TTL/CMOS Logic Compatible
GND-to-V+ Analog Signal Dynamic Range
Low Power Consumption (<12µW)
Low Crosstalk: -86dB @ 1MHz
Low Off-Isolation: -58dB @ 1 MHz
Wide Bandwidth: > 100 MHz
Small QSOP-16 Package Saves Board Area
Description
The PS4066/PS4066A are improved SPST CMOS analog
switches ideal for low-distortion audio switching. These high pre-
cision, medium voltage switches were designed to operate with
single-supplies from +3V to 16V. They are fully specified with
+12V, +5V, and +3V supplies. The PS4066/PS4066A has four
normally open (NO) switches. Each switch conducts current
equally well in either direction when on. In the off state each
switch blocks voltages up to the power-supply rails.
With +12V power supply, the PS4066/PS4066A guarantee <45Ω
on-resistance. On-resistance matching between channels is within
2Ω (PS4066). On-resistance flatness is less than 4Ω (PS4066A)
over the specified range. The PS4066A guarantees low leakage
currents (<100pA @ 25oC, <6nA @ +85oC) and fast switching
speeds (tON < 175ns). ESD sensitivity rating is >2,000V per
MIL-STD 883, Method 3015.7
Both devices are available in PDIP-14, narrow-body SOIC-14,
and QSOP-16 packages. Available temperature ranges are: com-
mercial (0oC to 70oC), and industrial (-40oC to +85oC).
For operation below 5V, the PI5A101/PI5A391/PI5A392 are also
recommended.
Applications
•
•
•
•
•
•
Instrumentation, ATE
Sample-and-Holds
Audio Switching and Routing
Telecommunication Systems
PBX, PABX
Battery-Powered Systems
Functional Diagrams, Pin Configurations, and Truth Table
Logic
0
1
Switch
O FF
ON
Top View
PDIP/SO
N.C. = No Internal Connection
Switches shown for logic “0” input
Top View
QSOP
1
PS8184A
10/15/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Absolute Maximum Ratings
Voltages Referenced to GND
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
V
IN
, V
COM
, V
NC
, V
NO
(Note 1) . . . . . . . . -2V to (V+) +2V
or 30mA, whichever occurs first
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, COM, NO, NC
(pulsed at 1ms, 10% duty cycle) . . . . . . . . . . . . . . . . 100mA
ESD per Method 3015.7 . . . . . . . . . . . . . . . . . . . . . . >2000V
Thermal Information
Continuous Power Dissipation (T
A
= +70
º
C)
Plastic DIP (derate 10.5mW/
º
C above +70
º
C) . . . . . . 800mW
SO and QSOP (derate 8.7mW/
º
C above +70
º
C) . . . . . 650mW
Storage Temperature . . . . . . . . . . . . . . . . . . . -65
º
C to +150
º
C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . +300
º
C
Note
Signals on NC, NO, COM, or IN exceeding V+ or GND are
clamped by internal diodes. Limit forward diode current to 30mA.
Caution:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied.
Electrical Specifications - Single +12V Supply
(V+ = 12V ±10%, GND = 0V, V
INH
= 4V, V
INL
= 0.8V)
Parame te r
Analog Switch
Analog Signal
Range
(3)
On Resistance
Symbol
Conditions
Te mp. (°C) M in
(1)
Typ
(2)
M ax
(1)
Units
V
ANALOG
R
ON
V+ = 12V, I
COM
= 2mA,
V
NO
= 10V
V+ = 12V, I
COM
= 2mA
V
NO
= 10V
PS4066
PS4066A
Full
25
Full
25
Full
0
12
V+
45
55
0.5
0.5
4
2
6
2
4
6
V
On- Resistance Match
Between Channels
(4)
On- Resistance
Flatness
(5)
NO or NC Off
Leakage Current
(6)
COM Off Leakage
Current
(6)
∆R
ON
Ω
R
FLAT(ON)
I
NO(OFF)
I
NC(OFF)
I
COM(OFF)
OR
V+ = 12V, I
COM
= 2mA,
V
NO
= 10V, 5V, 1V
V+ = 12V, V
COM
= 0V,
V
NO
= 10V
V+ = 12V, V
COM
= 0V,
V
NO
= 10V
PS4066
PS4066A
PS4066
PS4066A
25
Full
25
Full
25
Full
PS4066
PS4066A
25
Full
-1
- 0.1
-6
-1
- 0.1
-6
-2
- 0.2
- 12
1
0.1
6
1
0.1
6
2
0.2
12
nA
COM On Leakage
Current
(6)
I
COM(ON)
V+ = 12V, V
COM
= 10V,
V
NO
= 10V
2
PS8184A
10/15/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Electrical Specifications - Single +12V Supply
(continued)
(V+ = 12V ±10%, GND = 0V, V
INH
= 4V, V
INL
= 0.8V)
Parame te r
Logic Input
Input Current with
Input Voltage High
Input Current with
Input Voltage Low
D ynamic
Turn- O n Time
Turn- O ff Time
O n- Channel
Bandwidth
Charge Injection
(3)
O ff Isolation
Crosstalk
(8)
NO Capacitance
CO M O ff
Capacitance
CO M O n
Capacitance
Supply
Positive Supply
Current
Total Harmonic
Distortion
Symbol
Conditions
Te mp (°C)
M in
(1)
Typ
(2)
M ax
(1)
Units
I
INH
I
INL
IN =5V, all others = 0.8V
Full
IN = 0.8V, all others =5V
- 0.5
- 0.5
0.005
0.005
0.5
0.5
µA
t
ON
t
OFF
BW
Q
O IRR
X
TALK
C
(OFF)
25
V
COM
= 10V, Figure 2
Full
25
Full
Signal = 0dbm
Figure 4, 50
Ω
in and out
C
L
=1nF, V
GEN
= 0V, R
GEN
= 0
Ω,
Figure 3
R
L
= 50
Ω
, C
L
= 5pF, f = 1 MHz, Figure 4
R
L
= 50
Ω
, C
L
= 5pF, f = 1 MHz, Figure 5
f =1 MHz, Figure 6
f =1 MHz, Figure 6
25
45
17
100
150
75
100
ns
100
2
- 58
- 86
9
9
22
10
MHz
pC
dB
pF
C
COM(ON)
f =1MHz, Figure 7
I+
THD
V
IN
= 0V or V+,
all channels on or off
-1
Full
0.001
0.03
1
µA
%
Notes:
1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in
this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
∆R
ΟΝ
= ∆R
ΟΝ
max
-
∆R
ΟΝ
min
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25ºC.
7. Off Isolation = 20log
10
[ V
COM
/ (V
NO
or V
NO
) ], V
COM
= 0utput, V
NC
/V
NO
= input to off switch
8. Between any two switches.
3
PS8184A
10/15/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Electrical Specifications - Single +5V Supply
(V+ = +5V ±10%, GND = 0V, V
INH
= 2.4V, V
INL
= 0.8V)
Parame te r
Analog Switch
Analog Signal Range
(3)
O n- Resistance
On- Resistance
MatchBetween Channels
(4)
On- Resistance Flatness
(3,5)
NO Off Leakage
Current
(9)
CO M O ff Leakage
Curren
(9)
CO M O n Leakage
Current
(6)
D ynamic
Turn- On Time
Turn- O ff Time
O n- Channel Bandwidth
Charge Injection
(3)
Supply
Positive Supply Current
Symbol
V
ANALOG
R
ON
∆R
ON
R
FLAT(ON)
Conditions
Te mp (°C)
Full
M in
(1)
0
Typ
(2)
M ax
(1)
V+
Units
V
V+ = 4.5V, I
COM
= - 1mA,
V
NO
= 3.5V
V+ =5V, I
COM
= - 1mA,
V
NO
= 3V
V+ = 5V, I
COM
= - 1mA,
V
NO
= 1V, 3V
V+ = 5.5V, V
COM
= 0V,
V
NO
= 4.5V
V+ = 5.5V, V
COM
= 0V,
V
NO
= 4.5V
V+ = 5.5V, V
COM
= 5V
V
NO
= 4.5V
PS4066
PS4066A
PS4066
PS4066A
PS4066
PS4066A
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
25
-1
- 0.1
-6
-1
- 0.1
-6
-2
- 0.2
- 12
22
0.3
4
75
100
4
12
6
8
1
0.1
6
1
0.1
6
2
0.2
12
nA
Ω
I
NO(OFF)
I
COM(OFF)
I
COM(ON)
t
ON
V
NO
= 3V
t
OFF
BW
Q
Signal = 0dBm, 50
Ω
in and out
Figure 4
C
L
= 1nF, V
GEN
= 0V,
R
GEN =
0V, Figure 3
65
30
125
175
75
125
ns
Full
25
Full
25
25
100
1
MHz
10
pC
I+
V+ = 5.5V, V
IN
= 0V or V+,
all channels on or off
Full
-1
1
µA
4
PS8184A
10/15/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Electrical Specifications - Single +3V Supply
(V+ = +2.7V to 3.3V, GND = 0V, V
I
NH
= 2.4V, V
INL
= 0.8V)
Parame te r
Analog Switch
Analog Signal Range
(3)
Channel O n- Resistance
D ynamic
Turn- O n- Time
(3)
Turn- O ff- Time
(3)
Charge Injection
(3)
Supply
Positive Supply Current
Symbol
Conditions
Te mp°C M in.
(1)
Typ
(2)
M ax.
(1)
Units
V
ANALOG
R
ON
V+ = 3V, I
COM
= - 1mA,
V
NO
= 1.5V
25
Full
25
Full
25
Full
25
0
V+
170
225
80
40
185
230
150
200
2
10
V
Ω
t
ON
t
(OFF)
Q
V+ =3V, V
NO
= 1.5V
V+ =3V, V
NO
= 1.5V
C
L
= 1nF, V
GEN
= 0V,
R
GEN
= 0V
V+ = 3.3V, V
IN
= 0V or V+,
all channels on or off
ns
pC
I+
Full
-1
0.001
1
µA
Notes:
1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in
this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
∆R
ΟΝ
= ∆R
ΟΝ
max
-
∆R
ΟΝ
min
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25ºC.
7. Off Isolation = 20log
10
[ V
COM
/ (V
NO
or V
NO
) ], V
COM
= 0utput, V
NC
/V
NO
= input to off switch
8. Between any two switches.
5
PS8184A
10/15/98
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