74AC08PC_NL datasheet, PDF - EEWORLD Datasheet

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74AC08PC_NL: DescriptionAC SERIES, QUAD 2-INPUT AND GATE, PDSO14; Categorylogic logic; File Size101KB，7 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74AC08PC_NL Overview

AC SERIES, QUAD 2-INPUT AND GATE, PDSO14

74AC08PC_NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	unknow
series	AC
JESD-30 code	R-PDIP-T14
length	19.18 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.012 A
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	RAIL
power supply	3.3/5 V
Prop。Delay @ Nom-Su	10 ns
propagation delay (tpd)	10 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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74AC08 • 74ACT08 Quad 2-Input AND Gate

November 1988

Revised February 2005

74AC08 • 74ACT08

Quad 2-Input AND Gate

General Description

The AC/ACT08 contains four, 2-input AND gates.

Features

reduced by 50% on 74AC only

Outputs source/sink 24 mA

Ordering Code:

Order Number

74AC08SC

74AC08SJ

74AC08MTC

74AC08MTCX_NL

(Note 1)

74AC08PC

74AC08PC_NL

(Note 1)

74ACT08SC

74ACT08SCX_NL

(Note 1)

74ACT08MTC

74ACT08MTCX_NL

(Note 1)

74ACT08PC

74ACT08PC_NL

(Note 1)

Package

Number

M14A

M14D

MTC14

N14A

M14A

MTC14

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in Tape and Reel.)

Pb-Free package per JEDEC J-STD-020B.

Note 1:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Pin Names

, B

FACT

is a trademark of Fairchild Semiconductor Corporation.

Description

Inputs

Outputs

DS009914

www.fairchildsemi.com

74AC08PC_NL Related Products

	74AC08PC_NL	74AC08MTCX_NL	74AC08PCX	74AC08SJX	74ACT08MTCX_NL	74ACT08PC_NL	74ACT08PCX	74ACT08SCX_NL
Description	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14	AC SERIES, QUAD 2-INPUT AND GATE, PDSO14
series	AC	AC	AC	AC	ACT	ACT	AC	ACT
length	19.18 mm	5 mm	5 mm	10.2 mm	5 mm	19.18 mm	5 mm	8.6235 mm
Number of functions	4	4	4	4	4	4	4	4
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 Cel	85 °C	85 °C	85 °C	85 Cel	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 Cel	-40 °C	-40 °C	-40 °C	-40 Cel	-40 °C
surface mount	NO	YES	YES	YES	YES	NO	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	7.62 mm	4.4 mm	4.4 mm	5.3 mm	4.4 mm	7.62 mm	4.4 mm	3.9 mm
Is it Rohs certified?	conform to	conform to	-	conform to	conform to	conform to	-	conform to
Maker	Fairchild	Fairchild	-	Fairchild	Fairchild	Fairchild	-	Fairchild
Parts packaging code	DIP	TSSOP	-	SOP	TSSOP	DIP	-	SOIC
package instruction	DIP, DIP14,.3	TSSOP, TSSOP14,.25	-	SOP, SOP14,.3	TSSOP, TSSOP14,.25	DIP, DIP14,.3	-	SOP, SOP14,.25
Contacts	14	14	-	14	14	14	-	14
Reach Compliance Code	unknow	compli	-	compli	compli	compli	-	compli
JESD-30 code	R-PDIP-T14	R-PDSO-G14	-	R-PDSO-G14	R-PDSO-G14	R-PDIP-T14	-	R-PDSO-G14
Load capacitance (CL)	50 pF	50 pF	-	50 pF	50 pF	50 pF	-	50 pF
Logic integrated circuit type	AND GATE	AND GATE	-	AND GATE	AND GATE	AND GATE	-	AND GATE
MaximumI(ol)	0.012 A	0.012 A	-	0.012 A	0.024 A	0.024 A	-	0.024 A
Number of entries	2	2	-	2	2	2	-	2
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	DIP	TSSOP	-	SOP	TSSOP	DIP	-	SOP
Encapsulate equivalent code	DIP14,.3	TSSOP14,.25	-	SOP14,.3	TSSOP14,.25	DIP14,.3	-	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE	-	SMALL OUTLINE
method of packing	RAIL	TAPE AND REEL	-	TAPE AND REEL	TAPE AND REEL	RAIL	-	TAPE AND REEL
power supply	3.3/5 V	3.3/5 V	-	3.3/5 V	5 V	5 V	-	5 V
Prop。Delay @ Nom-Su	10 ns	10 ns	-	10 ns	10 ns	10 ns	-	10 ns
propagation delay (tpd)	10 ns	10 ns	-	10 ns	10 ns	10 ns	-	10 ns
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Schmitt trigger	NO	NO	-	NO	NO	NO	-	NO
Maximum seat height	5.08 mm	1.2 mm	-	2.1 mm	1.2 mm	5.08 mm	-	1.753 mm
Maximum supply voltage (Vsup)	6 V	6 V	-	6 V	5.5 V	5.5 V	-	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	-	2 V	4.5 V	4.5 V	-	4.5 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-	3.3 V	5 V	5 V	-	5 V
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS	-	CMOS
Terminal pitch	2.54 mm	0.65 mm	-	1.27 mm	0.65 mm	2.54 mm	-	1.27 mm
Base Number Matches	1	1	-	1	1	1	-	1
JESD-609 code	-	e3	-	e3	e3	e3	-	e3
Peak Reflow Temperature (Celsius)	-	260	-	260	260	NOT APPLICABLE	-	260
Terminal surface	-	Matte Tin (Sn)	-	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	-	MATTE TIN
Maximum time at peak reflow temperature	-	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT APPLICABLE	-	NOT SPECIFIED

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