P1.4
P1.3 P0.1
P1.2
P0.0
P1.1
VDD
P1.0
VSS RESET* P3.7 AGND RSVD VREF RSVD CEBin AVCC
CEWay™ is a family of chips
developed by DOMOSYS Corporation to meet
the requirements of the residential and
commercial local area networks (LANs). The
CEWay PL-One is the ideal device for simple
nodes, such as switches, actuators and
sensors. It integrates the complete Physical
Layer of the CEBus® standard (EIA-600) and
an M8052 core microcontroller. It provides you
with all of the resources you need to embed
the upper layers of the CEBus standard and
the user application into a single-chip solution.
The CEWay PL-One is designed for superior
performance in noisy power line environments.
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
P1.5
VDD
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
RSVD
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
VSS
P1.6
10
11
12
13
14
15
16
17
18
19
60
59
VSS
CEBout
RSVD
RSVD
PSEN*
ALE
RSVD
VDD
SELCLK
Domosys Corp.
58
57
56
55
54
53
52
CEWay
PL - One
TM
CW00I0A
51
50
49
48
47
46
45
44
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
CEBAM
TEST
20
21
22
23
24
25
703123
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P1.7
VDD
P2.6
VDD
P2.7
XTAL2 XTAL1 RSVD VSS
P3.3 RSVD
P3.0
P3.6
P3.4 RSVD P3.1
P3.5
Figure 1 Pin-out for CEWay PL-One
Features
•
CEBus power line Physical Layer
•
Power line medium dependent
Physical and Symbol Encoding
Sublayers
•
Proprietary DSP for superior signal
Reception in noisy environments
•
M8052 core microcontroller
•
4 SFRs for communication between
PLSES and M8052
•
Up to 64 KB of external data memory
•
256 bytes of internal data memory
•
Up to 64 KB of external code memory
(can be extended with bank switching)
•
Three 16-bit timer/counters
•
Full-duplex serial port
•
15 I/O pins
•
68-pin PLCC package
•
Industrial operating temperature range
D-CW-0100-04
Page 1 of 56
March 2000
CEWay™ PL-One Data Sheet
CEWay PL-One Block Diagram
SELCLK
RESET*
PSEN*
ALE
P0
P1
P2
P3
CEBout
Transmitter
SFRs
CEBAM
Symbol
Encoding
M8052
Core
PLSE Interrupt
RAM
256
Bytes
Power
Supply
OSC
CEBin
Receiver
XTAL2
Figure 2 CEWay PL-One Block Diagram
D-CW-0100-04
XTAL1
RSVD
AVCC
AGND
VREF
VDD
TEST
VSS
NC
Page 2 of 56
March 2000
CEWay™ PL-One Data Sheet
Pin Descriptions
Table 1 CEWay PL-One Pin Descriptions
Symbol
P0.0 – P0.7
P1.0 – P1.7
P2.0 – P2.7
P3.0, P3.1
P3.3 – P3.7
XTAL2
PIN
Description
5, 7, 12, 13,
Port 0:
8-bit bi-directional I/O port
14, 15, 16, 17 Port Pin
Alternative Function
P0.0
A/D0
P0.1
A/D1
P0.2
A/D2
P0.3
A/D3
P0.4
A/D4
P0.5
A/D5
P0.6
A/D6
P0.7
A/D7
2, 4, 6, 8, 9,
Port 1:
8-bit bi-directional I/O port
10, 26, 27
Port Pin
Alternative Function
P1.0
T2
P1.1
T2EX
P1.2
-
P1.3
-
P1.4
-
P1.5
-
P1.6
-
P1.7
-
19, 20, 21, 22,
Port 2:
8-bit bi-directional I/O port
23, 24, 29, 31 Port Pin
Alternative Function
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
P2.6
A14
P2.7
A15
38, 42, 36, 40,
Port 3:
7-bit I/O port. 2 bi-directional pins, 3 outputs, and 2 inputs.
43, 39, 67
Output pins always read as 0.
Port Pin
Alternative Function
Direction
P3.0
RxD
Bi-directional
P3.1
TxD
Bi-directional
P3.2
INT0: Not available externally, N/A
used for PLSES Interrupt.
P3.3
INT1
Input
P3.4
T0
Output
P3.5
T1
Input
P3.6
WR*
Output
P3.7
RD*
Output
32
Crystal 2: Output to the inverting oscillator amplifier that forms the
oscillator.
D-CW-0100-04
Page 3 of 56
March 2000
Symbol
XTAL1
CEBAM
CEBOUT
CEBIN
SELCLK
PSEN*
ALE
VREF
RESET*
PIN
33
CEWay™ PL-One Data Sheet
Description
Crystal 1: Input to the inverting oscillator amplifier that forms the
oscillator.
45
Output: Digital output used to enable and disable the transmit
amplifier.
59
CEBus power line signal output
62
CEBus power line signal input
52
SELCLK: Must be connected to VDD if 14.31818 MHz is used.
Connected to VSS if 21.4772 MHz is used.
56
PSEN*: Reads strobe to the external program memory via Port 0
and Port2.
55
ALE: Latches the low byte of the address during access of external
memory in normal operation.
64
Input for analog reference. A 1
µF
capacitance must be put
between this pin and AGND.
68
Reset: A LOW on this pin for 24 machine cycles and while the
oscillator is running resets the device. This pin has an internal pull-
up resistor. Note that, unlike most 8051 devices, no internal
Schmitt Trigger is present on this pin.
66
Ground: 0 volt Analog Reference
3, 11, 28, 30, Power Supply: Digital 5 volts
53
1, 25, 35,
Ground: 0 volt Digital Reference
51,60
61
Power Supply: Analog 5 volts
18, 34, 37, 41, Reserved - Must be connected to VSS.
46, 47, 48, 49,
50, 54, 57, 58,
63, 65
44
TEST: Must be connected to VSS.
AGND
VDD
VSS
AVCC
RSVD
TEST
D-CW-0100-04
Page 4 of 56
March 2000
CEWay™ PL-One Data Sheet
Electrical Specifications
Absolute Maximum Rating
1
Parameter
Supply Voltage
DC Input Voltage
DC Input Current
Storage Temperature
ESD Tolerance
1
Sym
V
DD
- V
ss
V
IN
I
IN
T
STG
Min
-0.3
-0.3
-10
-40
Max
7
VDD +0.3
+10
+125
2
Units
V
V
mA
O
C
kV
Test Conditions
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics -
Voltages are with respect to VSS unless otherwise stated
Parameter
Supply Voltage - Digital
Supply Voltage - Analog
Input Voltage (high)
Input Voltage (low)
Output Voltage (high)
Output Voltage (low)
Operating Current Digital
Operating Current Analog
Operating Temperature
2
3
Sym
VDD
AVCC
V
IH
V
IL
V
OH
V
OL
I
VDD
I
AVCC
T
O
Min
4.75
4.75
0.7VDD
VSS-0.3
2.4
Typ
2-3
5
5
Max
5.25
5.25
VDD+0.3
0.3VDD
0.4
35
15.5
+85
25
9.5
-40
Units
V
V
V
V
V
V
mA
mA
O
C
Test Conditions
I
OH
= 50
µA
I
OL
= 4 mA
f
CLK
= 14.318 MHz
f
CLK
= 14.318 MHz
Typical figures are at 25 OC and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
AC Electrical Characteristics
Parameter
CEBout Output Voltage
CEBout Load Impedance
CEBin Input Impedance
Clock Frequency
5
Pin Capacitance XTAL1,XTAL2
Input Pin Capacitance
Output Pin Capacitance
4
5
Sym
V
CEBout
ZL
CEBout
Zin
CEBin
f
CLK
C
XTAL
C
I
C
o
Min
5
40
14.31818
Typ
4
3.5
68
0.8
8
8
Max
140
21.4772
Units
V p-p
k
Ω
k
Ω
MHz
pF
pF
pF
Test Conditions
f
CLK
= 14.318 MHz
f
CLK
= 14.318 MHz
Typical figures are at 25 OC and are for design aid only: not guaranteed and not subject to production testing.
Clock frequency can only be either 14.31818 or 21.4772 MHz for proper chirp timing.
D-CW-0100-04
Page 5 of 56
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