PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
Rev. 02 — 19 July 2006
Product data sheet
1. General description
The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I
2
C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).
The device is fully configurable: output ports can be programmed to be totem-pole or
open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I
2
C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).
The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.
The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.
The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.
The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the
−40 °C
to +85
°C
industrial temperature range.
2. Features
I
1 MHz Fast-mode Plus I
2
C-bus serial interface
I
Compliant with I
2
C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
I
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I
40 configurable I/O pins that default to inputs at power-up
I
Outputs:
N
Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink)
with controlled edge rate output structure. Default to totem-pole on power-up.
N
Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be
programmed to active HIGH through the I
2
C-bus. Defaults to OE on power-up.
N
Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time respectively. Defaults to
Acknowledge on power-up.
I
Inputs:
N
Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
N
Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
N
Polarity Inverter register allows inversion of the polarity of the I/O pins when read
I
Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert
Response Address’ sequence. Own slave address sent when sequence initiated.
I
Active LOW Reset (RESET) input pin resets device to power-up default state
I
GPIO All Call address allows programming of more than one device at the same time
with the same parameters
I
64 programmable slave addresses using 3 address pins
I
Readable Device ID (manufacturer, device type and revision)
I
Designed for live insertion in PICMG applications
N
Minimize line disturbance (I
OFF
and power-up 3-state)
N
Signal transient rejection (50 ns noise filter and robust I
2
C-bus state machine)
I
Low standby current
I
−40 °C
to +85
°C
operation
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: TSSOP56, and HVQFN56
3. Applications
I
I
I
I
I
I
I
I
Servers
RAID systems
Industrial control
Medical equipment
PLCs
Cell phones
Gaming machines
Instrumentation and test measurement
PCA9698_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
2 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
4. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9698DGG
PCA9698BS
Topside mark
PCA9698DGG
PCA9698BS
Package
Name
TSSOP56
HVQFN56
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8
×
8
×
0.85 mm
Version
SOT364-1
SOT684-1
5. Block diagram
OE
PCA9698
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
AD0
AD1
AD2
8-bit
ADDRESS
DECODER
read pulse 0
write pulse 0
INPUT/
OUTPUT
PORTS
BANK 0
BANK 1
SCL
SDA
LOW PASS
INPUT
FILTERS
I
2
C-BUS/SMBUS
CONTROL
BANK 2
BANK 3
IO4_0
IO4_1
IO4_2
IO4_3
IO4_4
IO4_5
IO4_6
IO4_7
8-bit
V
DD
V
SS
RESET
POWER-ON
RESET
read pulse 4
write pulse 4
INPUT/
OUTPUT
PORTS
BANK 4
INTERRUPT
MANAGEMENT
INT/SMBALERT
LP FILTER
002aab935
Remark:
All I/Os are set to inputs at power-up and RESET.
Fig 1. Block diagram of PCA9698
PCA9698_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
3 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
configuration port register data (Cx[y])
output port register data (Ox[y])
OE
OEPOL
I/O
configuration
register
data from
shift register
D
FF
write configuration
pulse
CK
Q
IOx_y
Q
OUTx
V
DD
data from
shift register
D
FF
write pulse
CK
STOP
pulse
Q
OCH
output port
register
D
FF
CK
INTERRUPT
MANAGEMENT
input port
register
D
FF
read pulse
CK
polarity inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
002aab936
Q
Mx[y]
INT
Q
input port
register data
(Ix[y])
Q
polarity inversion
register data
(Px[y])
On power-up or RESET, all registers return to default values.
Fig 2. Simplified schematic of the I/Os (IO0_0 to IO4_7)
PCA9698_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
4 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
6. Pinning information
6.1 Pinning
SDA
SCL
IO0_0
IO0_1
IO0_2
V
SS
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
56 RESET
55 INT/SMBALERT
54 IO4_7
53 IO4_6
52 IO4_5
51 V
SS
50 IO4_4
49 IO4_3
48 IO4_2
47 IO4_1
46 V
DD
45 IO4_0
44 IO3_7
43 IO3_6
42 IO3_5
41 IO3_4
40 IO3_3
39 V
SS
38 IO3_2
37 IO3_1
36 IO3_0
35 IO2_7
34 V
SS
33 IO2_6
32 IO2_5
31 IO2_4
30 OE
29 AD2
002aab932
IO0_6 10
V
SS
11
IO0_7 12
IO1_0 13
IO1_1 14
IO1_2 15
IO1_3 16
IO1_4 17
V
DD
18
IO1_5 19
IO1_6 20
IO1_7 21
IO2_0 22
V
SS
23
IO2_1 24
IO2_2 25
IO2_3 26
AD0 27
AD1 28
PCA9698DGG
Fig 3. Pin configuration for TSSOP56
PCA9698_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
5 of 47
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