PCK940L
Low voltage 1 : 18 clock distribution chip
Rev. 01 — 4 April 2006
Product data sheet
1. General description
The PCK940L is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS
output capabilities. The device features the capability to select either a differential
LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS
compatible and feature the drive strength to drive 50
Ω
series or parallel terminated
transmission lines. With output-to-output skews of 150 ps, the PCK940L is ideal as a clock
distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also
make the device ideal for supplying clocks for a high performance microprocessor based
design.
With a low output impedance of approximately 20
Ω,
in both the HIGH and LOW logic
states, the output buffers of the PCK940L are ideal for driving series terminated
transmission lines. With an output impedance of 20
Ω,
the PCK940L has the capability of
driving two series terminated transmission lines from each output. This gives the
PCK940L an effective fan-out of 1 : 36. If a lower output impedance is desired, please see
the PCK942C data sheet.
The differential LVPECL inputs of the PCK940L allow the device to interface directly with a
LVPECL fan-out buffer like the PCKEP111 to build very wide clock fan-out trees or to
couple to a high frequency clock source. The LVCMOS input provides a more standard
interface for applications requiring only a single clock distribution chip at relatively low
frequencies. In addition, the two clock sources can be used to provide for a test clock
interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLKSEL pin
will select the LVCMOS level clock input. All inputs of the PCK940L have internal
pull-up/pull-down resistors so they can be left open if unused.
The PCK940L is a single or dual supply device. The device power supply offers a high
degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V
core and 2.5 V outputs, as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP
package was chosen to optimize performance, board space and cost of the device. The
32-lead LQFP package has a 7 mm
×
7 mm body size with a conservative 0.8 mm pin
spacing.
2. Features
I
I
I
I
I
LVPECL or LVCMOS clock input
2.5 V LVCMOS outputs for Pentium II microprocessor support
150 ps maximum output-to-output skew
Maximum output frequency of 250 MHz at 3.3 V V
CC
32-lead LQFP packaging
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
I
Dual or single supply voltage:
N
Dual V
CC
supply voltage, 3.3 V core and 2.5 V output
N
Single 3.3 V V
CC
supply voltage for 3.3 V outputs
N
Single 2.5 V V
CC
supply voltage for 2.5 V I/O
3. Ordering information
Table 1.
Ordering information
Package
Name
PCK940LBD
LQFP32
Description
plastic low profile quad flat package; 32 leads;
body 7
×
7
×
1.4 mm
Version
SOT358-1
Type number
4. Functional diagram
PCK940L
PECL_CLK
PECL_CLK
LVCMOS_CLK
0
Q0
1
16
Q1 to Q16
LVCMOS_CLKSEL
(internal pull-down)
Q17
002aab887
Fig 1. Functional diagram of PCK940L
PCK940L_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 4 April 2006
2 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
5. Pinning information
5.1 Pinning
25 GND1
24 Q6
23 Q7
22 Q8
21 V
CC2
20 Q9
19 Q10
18 Q11
17 GND2
Q16 10
Q15 11
GND1 12
Q14 13
Q13 14
Q12 15
V
CC1
16
9
002aab888
29 V
CC1
32 Q0
31 Q1
30 Q2
28 Q3
27 Q4
GND1
GND2
LVCMOS_CLK
LVCMOS_CLKSEL
PECL_CLK
PECL_CLK
V
CC2
V
CC1
1
2
3
4
5
6
7
8
PCK940LBD
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2.
Symbol
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLKSEL
Q0 to Q17
Pin description
Pin
5
6
3
4
32, 31, 30, 28,
27, 26, 24, 23,
22, 20, 19, 18,
15, 14, 11, 10, 9
1, 12, 25
2, 17
8, 16, 29
7, 21
I/O
input
input
input
input
output
Type
LVPECL
LVPECL
LVCMOS
LVCMOS
LVCMOS
Description
reference clock input
reference clock input
(active LOW)
alternative reference clock
input
clock source select
clock outputs
GND1
GND2
V
CC1
V
CC2
-
-
-
-
Q17
supply
supply
supply
supply
26 Q5
output negative power supply
core negative power supply
output positive power supply
core positive power supply
PCK940L_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 4 April 2006
3 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
6. Functional description
Refer to
Figure 1 “Functional diagram of PCK940L”.
6.1 Function table
Table 3.
0
1
Table 4.
Supply pin
V
CC2
V
CC1
Function table
Input
PECL_CLK
LVCMOS_CLK
Power supply voltage
Voltage level
2.5 V or 3.3 V
±
5 %
2.5 V or 3.3 V
±
5 %
LVCMOS_CLKSEL
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
I
I
T
stg
Parameter
supply voltage
input voltage
input current
storage temperature
Conditions
Min
−0.3
−0.3
-
−40
Max
+3.6
V
DD
+ 0.3
±20
+125
Unit
V
V
mA
°C
8. Static characteristics
Table 6.
Static characteristics (3.3 V V
CC
, 3.3 V outputs)
T
amb
= 0
°
C to 70
°
C; V
CC2
= 3.3 V
±
5 %; V
CC1
= 3.3 V
±
5 %
Symbol
V
IH
V
IL
V
i(p-p)
V
ICR
V
OH
V
OL
I
I
C
i
C
PD
Z
o
I
CC(max)
Parameter
HIGH-level input voltage
LOW-level input voltage
peak-to-peak input voltage
common mode input voltage range
HIGH-level output voltage
LOW-level output voltage
input current
input capacitance
power dissipation capacitance
output impedance
maximum supply current
per output
Conditions
LVCMOS_CLK
LVCMOS_CLK
PECL_CLK
PECL_CLK
I
OH
=
−20
mA
I
OH
= 20 mA
Min
2.4
-
500
V
CC
−
1.4
2.4
-
-
-
-
18
-
Typ
-
-
-
-
-
-
-
4.0
10
23
0.5
Max
V
CC2
0.8
1000
V
CC
−
0.6
-
0.5
±200
-
-
28
1.0
Unit
V
V
mV
V
V
V
µA
pF
pF
Ω
mA
PCK940L_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 4 April 2006
4 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
Table 7.
Static characteristics (3.3 V V
CC
, 2.5 V outputs)
T
amb
= 0
°
C to 70
°
C; V
CC2
= 3.3 V
±
5 %; V
CC1
= 2.5 V
±
5 %
Symbol
V
IH
V
IL
V
i(p-p)
V
ICR
V
OH
V
OL
I
I
C
i
C
PD
Z
o
I
CC(max)
Parameter
HIGH-level input voltage
LOW-level input voltage
peak-to-peak input voltage
common mode input voltage range
HIGH-level output voltage
LOW-level output voltage
input current
input capacitance
power dissipation capacitance
output impedance
maximum supply current
per output
Conditions
LVCMOS_CLK
LVCMOS_CLK
PECL_CLK
PECL_CLK
I
OH
=
−20
mA
I
OH
= 20 mA
Min
2.4
-
500
V
CC
−
1.4
1.8
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
4.0
10
23
0.5
Max
V
CC2
0.8
1000
V
CC
−
0.6
-
0.5
±200
-
-
-
1.0
Unit
V
V
mV
V
V
V
µA
pF
pF
Ω
mA
Table 8.
Static characteristics (2.5 V V
CC
, 2.5 V output)
T
amb
= 0
°
C to 70
°
C; V
CC2
= 2.5 V
±
5 %; V
CC1
= 2.5 V
±
5 %
Symbol
V
IH
V
IL
V
i(p-p)
V
ICR
V
OH
V
OL
I
I
C
i
C
PD
Z
o
I
CC(max)
Parameter
HIGH-level input voltage
LOW-level input voltage
peak-to-peak input voltage
common mode input voltage range
HIGH-level output voltage
LOW-level output voltage
input current
input capacitance
power dissipation capacitance
output impedance
maximum supply current
per output
Conditions
LVCMOS_CLK
LVCMOS_CLK
PECL_CLK
PECL_CLK
I
OH
=
−20
mA
I
OH
= 20 mA
Min
2.0
-
500
V
CC
−
1.0
1.8
-
-
-
-
18
-
Typ
-
-
-
-
-
-
-
4.0
10
23
0.5
Max
V
CC2
0.8
1000
V
CC
−
0.6
-
0.5
±200
-
-
28
1.0
Unit
V
V
mV
V
V
V
µA
pF
pF
Ω
mA
PCK940L_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 4 April 2006
5 of 16
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