signal processing and servo control required by compact
disc players. At the same time as providing an EFM PLL
circuit, a 1-bit D/A converter, and an analog low-pass
filter the LC78622NE realizes an optimal cost-
performance tradeoff for low-end players by strictly
limiting functionality to basic signal-processing and servo
system functionality. The LC78622NE signal-processing
system provides demodulation of the EFM signal from the
pickup, de-interleaving, error detection and correction, and
digital filters that can prove useful in reducing the cost of
end products. The LC78622NE servo control system
processes servo commands sent from the control
microprocessor.
The LC78622NE is an improved version of the LC78622E
that adds 8× oversampling digital filters, three general-
purpose output ports (that also have specific shared
functions) and the PCCL pin (pin 34). However, some
handling of general-purpose ports differ from that of the
LC78622E, therefore care must be taken.(Refer to pages
16 and 21).
•
•
•
•
•
•
•
•
Functions
• Input signal processing: The LC78622NE takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
•
•
•
•
•
signal generated from the playback clock and the
reference clock
Frame synchronization signal detection, protection and
interpolation to assure stable data readout
EFM signal demodulation and conversion to 8-bit
symbol data
Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
Subcode Q signal output to a microprocessor over the
serial I/O interface after performing a CRC error check
(LSB first)
Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
Sets the C2 flags based on the C1 flags and a C2 check,
and then performs signal interpolation or muting
depending on the C2 flags. The interpolation circuit uses
a dual-interpolation scheme. The previous value is held
if the C2 flags indicate errors two or more times
consecutively.
Support for command input from a control
microprocessor: commands include track jump, focus
start, disk motor start/stop, muting on/off and track
count (8 bit serial input)
Built-in digital output circuits.
Arbitrary track counting to support high-speed data
access
D/A converter outputs with data continuity improved by
8× oversampling digital filters.
Built-in third-order
∑∆
D/A converters (An analog low-
pass filter is built in.)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
11999RM (OT) No. 6015-1/31
LC78622NE
Built-in digital attenuator (8 bits – alpha, 239 steps)
Built-in digital de-emphasis
Zero cross muting
Supports the implementation of a double-speed dubbing
function.
• Support for bilingual applications.
• General-purpose I/O ports: 5 pins
•
•
•
•
Package Dimensions
unit: mm
3159-QFP64E
[LC78622NE]
1.0
1.6
1.0
48
49
32
0.8
17.2
14.0
0.35
33
1.6
1.0
0.15
Features
• 5 V single-voltage power supply
17.2
14.0
0.8
17
1.0
64
1
16
3.0max
0.8
0.1
2.7
15.6
SANYO: QFP64E (QIP64E)
Equivalent Circuit Block Diagram
No. 6015-2/31
LC78622NE
Pin Assignment
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
max
V
IN
V
OUT
Pd max
Topr
Tstg
Conditions
Ratings
V
SS
– 0.3 to V
SS
+ 7.0
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
300
–20 to +75
–40 to +125
Unit
V
V
V
mW
°C
°C
No. 6015-3/31
LC78622NE
Allowable Operating Ranges
at Ta = 25°C, V
SS
= 0 V
Parameter
Symbol
V
DD
(1)
Supply voltage
V
DD
(2)
V
IH
(1)
V
IH
(2)
V
IL
(1)
Input low level voltage
V
IL
(2)
Data setup time
Data hold time
High level clock pulse width
Low level clock pulse width
Data read access time
Command transfer time
Subcode Q read enable time
Subcode read cycle time
Subcode read enable time
Port input data setup time
Port input data hold time
Port input clock setup time
Port output data delay time
Input level
Operating frequency range
Crystal oscillator frequency
t
SU
t
HD
t
WH
t
WL
t
RAC
t
RWC
t
SQE
t
SC
t
SE
t
CSU
t
CHD
t
RCQ
t
CDD
V
IN
(1)
V
IN
(2)
fop
f
X
Conditions
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
:
During normal-speed playback
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
:
During double-speed playback
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL
EFMIN
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL
EFMIN
COIN, RWC: Figure 1
COIN, RWC: Figure 1
SBCK, CQCK: Figures 1, 2 and 3
SBCK, CQCK: Figures 1, 2 and 3
SQOUT, PW: Figures 2 and 3
RWC: Figure 1
WRQ: Figure 2, with no RWC signal
SFSY: Figure 3
SFSY: Figure 3
CONT1 to CONT5, RWC: Figure 4
CONT1 to CONT5, RWC: Figure 4
RWC, CQCK: Figure 4
CONT1 to CONT8, RWC: Figure 5
EFMIN: Slice level control
X
IN
: Capacitor-coupled input
EFMIN
X
IN
, X
OUT
16.9344
1.0
1.0
10
400
400
400
100
1200
min
3.6
typ
max
5.5
Unit
V
3.6
0.7 V
DD
0.6 V
DD
0
0
400
400
400
400
0
1000
11.2
136
5.5
V
DD
V
DD
0.3 V
DD
0.4 V
DD
V
V
V
V
V
ns
ns
ns
ns
Input high level voltage
400
ns
ns
ms
µs
ns
ns
ns
ns
ns
Vp-p
Vp-p
MHz
MHz
Electrical Characteristics
at Ta = 25°C, V
DD
= 5 V, V
SS
= 0 V
Parameter
Current drain
Input high level current
Symbol
I
DD
I
IH
(1)
I
IH
(2)
Input low level current
I
IL
V
OH
(1)
Output high level voltage
V
OH
(2)
V
OH
(3)
V
OL
(1)
Output low level voltage
V
OL
(2)
V
OL
(3)
I
OFF
(1)
Output off leakage current
I
OFF
(2)
Charge pump output current
I
PDOH
I
PDOL
Conditions
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,
RWC, CQCK: TEST1: V
IN
= V
DD
TAI, TEST2 to TEST5, CS, PCCL: V
IN
= V
DD
= 5.5 V
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC,
CQCK: TAI, TEST1 to TEST5, CS, PCCL: V
IN
= 0 V
EFMO, CLV
+
, CLV
–
, V/P, PCK, FSEQ, TOFF,
TGL, JP
+
, JP
–
, EMPH/CONT6, EFLG, FSX: I
OH
= –1 mA
MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, PW,
SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to
CONT5: I
OH
= –0.5 mA
DOUT: I
OH
= –12 mA
EFMO,
V/P, PCK, FSEQ,
TOFF, TGL, JP
+
, JP
–
, EMPH/CONT6, EFLG, FSX:
I
OH
= 1 mA
CLV
–
,
MUTEL/CONT7, MUTER/CONT8,
C2F, SBSY, PW, SFSY, WRQ, SQOUT,
TST11, 16M, 4.2M, CONT1 to CONT5:
I
OH
= 2 mA
DOUT: I
OH
= 12 mA
PDO,
V
OUT
= V
DD
CLV
+
,
CLV
–
,
JP
+
,
JP
–
,
CONT1 to CONT5:
CLV
+
,
25
–5
4
min
typ
25
max
35
5
75
Unit
mA
µA
µA
µA
V
4
4.5
1
V
V
V
0.4
V
0.5
5
–5
64
–96
80
–80
96
–64
V
µA
µA
µA
µA
PDO, CLV
+
, CLV
–
, JP
+
, JP
–
, CONT1 to CONT5:
V
OUT
= 0 V
PDO: R
ISET
= 68 kΩ
PDO: R
ISET
= 68 kΩ
No. 6015-4/31
LC78622NE
One-Bit D/A Converter Analog Characteristics
at Ta = 25°C, V
DD
= LV
DD
= RV
DD
= 5 V, V
SS
= LV
SS
= RV
SS
= 0 V
Parameter
Total harmonic distortion
Symbol
THD + N
Conditions
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter (AD725D built in)
LCHO, RCHO; 1 kHz: –60 dB data input,
using the 20 kHz low-pass filter and the A filter
(AD725D built in)
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter and the A filter
(AD725D built in)
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter (AD725D built in)
87
min
typ
0.009
max
0.012
Unit
%
Dynamic range
DR
90
dB
Signal-to-noise ratio
S/N
93
95
dB
Crosstalk
CT
82
84
dB
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).
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