NB3N853501E
3.3 V LVTTL/LVCMOS 2:1
MUX to 4 LVPECL
Differential Clock Fanout
Buffer Outputs with Clock
Enable and Clock Select
Description
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MARKING
DIAGRAM
The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution
fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK
lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using
LVCMOS/LVTTL levels. Outputs are LVPECL levels and are
synchronously enabled by CLK_EN using LVCMOS/LVTTL levels
(HIGH to enable outputs, LOW to disable output).
Features
•
•
•
•
•
•
•
•
•
•
•
•
TSSOP−20
DT SUFFIX
CASE 948E
NB3N
501E
ALYWG
G
Four differential LVPECL Outputs
Two Selectable LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max.)
Device to Device Skew 250 ps (Max.)
Propagation Delay 2.0 ns (Max.)
Operating range: V
CC
= 3.3
±5%
V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 62 fs (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (−40
°
C to 85
°
C)
Pb−Free TSSOP20 Package
These are Pb−Free Devices
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 2
1
Publication Order Number:
NB3N853501E/D
NB3N853501E
V
EE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
CC
Q1
Q1
Q2
Q2
V
CC
Q3
Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Number
1
2
3
4
5, 6, 8, 9
6
10, 13, 18
11, 14, 16,
19
12, 15, 16,
20
Name
V
EE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
V
CC
Q[3:0]
Q[3:0]
LVPECL
LVPECL
LVCMOS /
LVTTL
Pulldown
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
Pullup
Pulldown
Pulldown
I/O
Open
Default
Description
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input)
Clock 0 Input. Float open when unused.
No Connect
Clock 1 Input. Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Invert Differential Outputs
True Differential Outputs
Table 2. FUNCTIONS
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Input Function
CLK0 input selected
CLK1 Input Selected
CLK0 input selected
CLK1 Input Selected
Output Function
Disabled
Disabled
Enabled
Enabled
Outputs
Qx
LOW
LOW
CLK0
CLK1
Qx
HIGH
HIGH
Invert of
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
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2
NB3N853501E
Figure 3. CLK_EN TIMING DIAGRAM
Table 3. ATTRIBUTES
(Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Human Body Model
Machine Model
Value
50 kW
50 kW
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
28 to 34
317 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 3)
Symbol
V
CC
V
in
C
in
I
out
T
A
T
stg
q
JA
q
JA
Supply Voltage
Input Voltage
Input Capacitance
Output Current
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
0 lfpm
TSSOP−20
Single−Layer
PCB (700 mm
2
,
2 oz)
Multi−Layer
PCB (700 mm
2
,
2 oz)
TSSOP−20
Continuous
Surge
Parameter
Condition 1
Condition 2
Rating
4.6
−0.5
v
V
I
v
V
CC
+ 0.5
4
50
100
−40
to
v
+85
−65
to +150
140
50
128
Unit
V
V
pF
mA
°C
°C
°C/W
°C/W
200 lfpm
94
q
JC
T
sol
Thermal Resistance (Junction−to−Case)
Wave Solder
(Note 4)
23 to 41
265
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
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3
NB3N853501E
Table 5. DC CHARACTERISTICS
V
CC
= 3.3
±5%
V (3.135 to 3.465 V), GND = 0 V, T
A
=
−40°C
to +85°C (Note 5)
Symbol
I
EE
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
VOUT
SWING
Power Supply Current
Input HIGH Voltage
Input LOW Voltage
Input High Current (V
CC
= V
in
= 3.456 V)
Input LOW Current (V
CC
= 3.456 V; V
in
= GND)
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing (peak−to−peak)
CLK0 CLK1
CLK_EN CLK_SEL
CLKx, CLK_SEL
CLK_EN
CLKx, CLK_SEL
CLK_EN
−5
−150
V
CC
−
1.4
V
CC
−
2.0
0.6
V
CC
−
0.9
V
CC
−
1.7
1.0
2
−0.3
−0.3
Characteristic
Min
Typ
Max
50
V
CC
+
0.3
1.3
0.8
150
5
Unit
mA
V
V
mA
mA
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50
W
to V
CC
−
2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise.
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NB3N853501E
Table 6. AC CHARACTERISTICS
V
CC
= 3.3
±5%
V (3.135 to 3.465 V), GND = 0 V, T
A
=
−40°C
to +85°C (Note 6)
Symbol
F
MAX
t
PD
tSKEW
DC
tSKEW
O−O
tSKEW
D−D
t
JIT
t
r
/t
f
Maximum Operating Frequency
Propagation Delay
Duty Cycle Skew same path similar conditions at 50 MHz
Output to Output Skew Within A Device
Device−to−Device Skew similar path and conditions
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6.
Output rise and fall times @ 266 MHz (20% and 80% points)
240
0.062
700
Characteristic
Min
0
0.9
48
50
Typ
Max
266
2.0
52
30
250
Unit
MHz
ns
%
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50
W
to V
CC
−
2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise. Measured from Input Midpoint
(V
DD
/2) to differential Output crosspoints, see Figure 5.
Figure 4. Typical Test Setup and Termination for Evaluation. The V
CC
of 2.0 V and V
EE
of
−1.3
±0.165
V Split
supply allows a direct connection to an oscilloscope 50
W
impedance input module. Also reference AND8020.
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5
Embedded System
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