AT25F512 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> AT25F512

AT25F512: Description128K X 8 SPI BUS SERIAL EEPROM, PDSO8; Categorystorage; File Size248KB，18 Pages; ManufacturerAtmel (Microchip)

Download Datasheet Parametric Compare View All

AT25F512 Overview

128K X 8 SPI BUS SERIAL EEPROM, PDSO8

AT25F512 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	2.7 V
Rated supply voltage	3 V
maximum clock frequency	20 MHz
Processing package description	0.150 INCH, Plastic, MS-012AA, SOIC-8
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	SMALL OUTLINE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	1.27 mm
terminal coating	tin lead
Terminal location	pair
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	128K × 8
storage density	1.05E6 deg
operating mode	Synchronize
Number of digits	131072 words
Number of digits	128K
Memory IC type	bus serial electrically erasable read-only memory
serial parallel	serial
Maximum TWC of write cycle	10 ms

Preview

Download Datasheet

View All

Features

•

Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 (0,0) and 3 (1,1)

20 MHz Clock Rate

Byte Mode and 256-byte Page Mode for Program Operations

Sector Architecture:

– Two Sectors with 32K Bytes Each (512K)

– Four Sectors with 32K Bytes Each (1M)

– 128 Pages per Sector

Product Identification Mode

Low-voltage Operation

– 2.7 (V

= 2.7V to 3.6V)

Sector Write Protection

Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

Self-timed Program Cycle (60 µs/Byte Typical)

Self-timed Sector Erase Cycle (1 second/Sector Typical)

Single Cycle Reprogramming (Erase and Program) for Status Register

High Reliability

– Endurance: 10,000 Write Cycles Typical

Lead-free Devices Available

8-lead JEDEC SOIC and 8-lead SAP Packages

•

SPI Serial

Memory

512K (65,536 x 8)

1M (131,072 x 8)

Description

The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash

memory organized as 65,536/131,072 words of 8 bits each. The device is optimized

for use in many industrial and commercial applications where low-power and low-volt-

age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead

JEDEC SOIC and 8-lead SAP packages.

The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a

3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK). All write cycles are completely self-timed.

BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or

entire memory array (512K) is enabled by programming the status register. Separate

write enable and write disable instructions are provided for additional data protection.

Hardware data protection is provided via the WP pin to protect against inadvertent

write attempts to the status register. The HOLD pin may be used to suspend any serial

communication without resetting the serial sequence.

AT25F512

AT25F1024

Pin Configurations

Pin Name

SCK

GND

VCC

HOLD

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial Input

VCC

HOLD

SCK

GND

8-lead SOIC

VCC

HOLD

SCK

8-lead SAP

GND

Bottom View

Rev. 1440P–SEEPR–6/04

AT25F512/1024

Serial Interface

Description

MASTER:

The device that generates the serial clock.

SLAVE:

Because the Serial Clock pin (SCK) is always an input, the AT25F512/1024

always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25F512/1024 has separate pins designated for

data transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25F512/1024, and the serial output pin (SO) will remain in a high impedance state

until the falling edge of CS is detected again. This will reinitialize the serial

communication.

CHIP SELECT:

The AT25F512/1024 is selected when the CS pin is low. When the

device is not selected, data will not be accepted via the SI pin, and the serial output pin

(SO) will remain in a high impedance state.

HOLD:

The HOLD pin is used in conjunction with the CS pin to select the

AT25F512/1024. When the device is selected and a serial sequence is underway,

HOLD can be used to pause the serial communication with the master device without

resetting the serial sequence. To pause, the HOLD pin must be brought low while the

SCK pin is low. To resume serial communication, the HOLD pin is brought high while the

SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored

while the SO pin is in the high impedance state.

WRITE PROTECT:

The 25F512/1024 has a write lockout feature that can be activated

by asserting the write protect pin (WP). When the lockout feature is activated, locked-out

sectors will be READ only. The write protect pin will allow normal read/write operations

when held high. When the WP is brought low and WPEN bit is “1”, all write operations to

the status register are inhibited. WP going low while CS is still low will interrupt a write to

the status register. If the internal status register write cycle has already been initiated,

WP going low will have no effect on any write operation to the status register. The WP

pin function is blocked when the WPEN bit in the status register is “0”. This will allow the

user to install the AT25F512/1024 in a system with the WP pin tied to ground and still be

able to write to the status register. All WP pin functions are enabled when the WPEN bit

is set to “1”.

1440P–SEEPR–6/04

AT25F512 Related Products

	AT25F512	AT25F1024	AT25F512_04	AT25F512N-10SI-2.7	AT25F512Y4-10YU-2.7	AT25F512N-10SU-2.7	AT25F1024Y4-10YU-2.7	AT25F1024N-10SU-2.7	AT25F1024N-10SI-2.7
Description	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8	128K X 8 SPI BUS SERIAL EEPROM, PDSO8
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	8	8	8	8	8	8	8	8	8
Maximum operating temperature	85 Cel	85 Cel	85 Cel	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
surface mount	Yes	Yes	Yes	YES	YES	YES	YES	YES	YES
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	NO LEAD	GULL WING	NO LEAD	GULL WING	GULL WING
Terminal location	pair	pair	pair	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
memory width	8	8	8	8	8	8	8	8	8
organize	128K × 8	128K × 8	128K × 8	64KX8	64KX8	64KX8	128KX8	128KX8	128KX8
Is it lead-free?	-	-	-	Contains lead	Lead free	Lead free	-	Lead free	Contains lead
Is it Rohs certified?	-	-	-	incompatible	conform to	conform to	conform to	conform to	incompatible
Parts packaging code	-	-	-	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	-	-	-	0.150 INCH, PLASTIC, MS-012AA, SOIC-8	HVSON, SOLCC8,.25	0.150 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-012AA, SOIC-8	HVSON, SOLCC8,.25	0.150 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-012AA, SOIC-8	SOP, SOP8,.25
Contacts	-	-	-	8	8	8	8	8	8
Reach Compliance Code	-	-	-	unknow	compliant	unknown	compliant	unknow	unknow
ECCN code	-	-	-	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum clock frequency (fCLK)	-	-	-	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz
Durability	-	-	-	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles
JESD-30 code	-	-	-	R-PDSO-G8	R-XDSO-N8	R-PDSO-G8	R-XDSO-N8	R-PDSO-G8	R-PDSO-G8
JESD-609 code	-	-	-	e0	e4	e3	e4	e3	e0
length	-	-	-	4.9 mm	6 mm	4.9 mm	6 mm	4.9 mm	4.9 mm
memory density	-	-	-	524288 bi	524288 bit	524288 bit	1048576 bit	1048576 bi	1048576 bi
Memory IC Type	-	-	-	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
Humidity sensitivity level	-	-	-	1	3	1	3	1	1
word count	-	-	-	65536 words	65536 words	65536 words	131072 words	131072 words	131072 words
character code	-	-	-	64000	64000	64000	128000	128000	128000
Operating mode	-	-	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Package body material	-	-	-	PLASTIC/EPOXY	UNSPECIFIED	PLASTIC/EPOXY	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	-	SOP	HVSON	SOP	HVSON	SOP	SOP
Encapsulate equivalent code	-	-	-	SOP8,.25	SOLCC8,.25	SOP8,.25	SOLCC8,.25	SOP8,.25	SOP8,.25
Package shape	-	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	-	-	SMALL OUTLINE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE
Parallel/Serial	-	-	-	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL
Peak Reflow Temperature (Celsius)	-	-	-	240	260	260	260	260	240
power supply	-	-	-	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V
Programming voltage	-	-	-	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Certification status	-	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	-	1.75 mm	0.9 mm	1.75 mm	0.9 mm	1.75 mm	1.75 mm
Serial bus type	-	-	-	SPI	SPI	SPI	SPI	SPI	SPI
Maximum standby current	-	-	-	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A
Maximum slew rate	-	-	-	0.03 mA	0.03 mA	0.03 mA	0.03 mA	0.03 mA	0.03 mA
Maximum supply voltage (Vsup)	-	-	-	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	-	-	-	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	-	-	-	3 V	3 V	3 V	3 V	3 V	3 V
technology	-	-	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal surface	-	-	-	Tin/Lead (Sn/Pb)	Gold (Au) - with Nickel (Ni) barrier	Matte Tin (Sn)	Gold (Au) - with Nickel (Ni) barrier	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal pitch	-	-	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Maximum time at peak reflow temperature	-	-	-	30	40	40	40	40	30
type	-	-	-	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	-	-	-	3.9 mm	4.9 mm	3.9 mm	4.9 mm	3.9 mm	3.9 mm
write protect	-	-	-	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE
Base Number Matches	-	-	-	-	1	1	1	1	1

Recommended Resources

Concentrated typical circuit of reference voltage b

500Hz bandpass filter circuit

Multi-terminal regulator 5G14 circuit diagram

Automatic air freshener circuit

Filter (regulator) circuits for different application fields

Function oscillator with wide frequency range

n1000060? ? ? ? ? ? ? ? ? ? ? ? ?: There is too little information. Does anyone have the program or information?...; sonic1007 Sensor

09 National Electronic Design Competition Prediction Questions: [i=s]This post was last edited by paulhyde on 2014-9-15 09:39[/i] I saw the predicted topics for the 2009 National Undergraduate Electronic Design Competition on the Internet not long ago. It includes...; skymaster Electronics Design Contest

[Help] How to use 135 to count orthogonal pulses: I would like to ask the moderator and all the experts how to use MSP135 to perform addition and subtraction counting of orthogonal (AB phase) pulses. Thank you....; wenfengcom Microcontroller MCU

Last day! Live broadcast with prizes | RSL15 - ON Semiconductor's more efficient, smarter and safer BLE 5.2 Bluetooth chip: Live broadcast time: March 31, 2022 (Thursday) 10:00-11:30 amLive Topic: RSL15 - ON Semiconductor's More Efficient, Smarter and Safer BLE 5.2 Bluetooth Chip Register for an appointmentLive broadcast c...; EEWORLD社区 RF/Wirelessly

Is it necessary to switch modes when nesting arm interrupts?: I see that in arm's irq interrupt handler, the scene is protected in the assembly code, and then the cpsr is modified to clear the I_bit, and then the IRQ mode is switched to the sys mode, and then th...; eekingking ARM Technology

Studying the road to electric motor driving-1: [i=s]This post was last edited by MianQi on 2021-6-11 17:57[/i]This is the second lecture in this series - Movement and Rotation:...; MianQi Motor Drive Control（Motor Control）

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components