Features
•
Three High-side and Three Low-side Drivers
•
Outputs Freely Configurable as Switch, Half Bridge or H-bridge
•
Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors,
•
•
•
•
•
•
•
•
•
•
•
Capacitors and Inductors
0.6A Continuous Current Per Switch
Low-side: R
DSon
< 1.5Ω Versus Total Temperature Range
High-side: R
DSon
< 2.0Ω Versus Total Temperature Range
Very Low Quiescent Current I
S
< 20 µA in Standby Mode
Outputs Short-circuit Protected
Overtemperature Prewarning and Protection
Undervoltage and Overvoltage Protection
Various Diagnosis Functions Such as Shorted Output, Open Load,
Overtemperature and Power Supply Fail
Serial Data Interface
Daisy Chaining Possible
SSO20 Package
Dual Triple
DMOS Output
Driver with
Serial Input
Control
T6817
1. Description
The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technol-
ogy. It can be used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design is especially supportive of
H-bridges applications to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnosis functions and a very low quiescent current in
standby mode open a wide range of applications. Meeting automotive qualifications in
the area of conducted interferences, EMC protection and 2 kV ESD protection provide
added value and enhanced quality for the exacting requirements of automotive
applications.
Rev. 4670C–BCD–09/05
Figure 1-1.
Block Diagram
HS3
12
HS2
14
HS1
16
Osc
Fault
detect
Fault
detect
Fault
detect
VS
6
VS
DI
2
S
C
T
O
L
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
V
S
S
I
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
7
CLK
OV
-
protection
4
V
S
Input register
CS
Vcc
VCC
19
3
Output register
Serial interface
Control
logic
H
S
1
L T
S P
1
UV
protection
-
INH
5
P
S
F
I
N
H
S
C
D
n.
u.
n.
u.
n. n.
u. u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
Power-on
reset
GND
1
GND
10
GND
11
DO
18
Vcc
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
17
GND
13
GND
8
LS3
LS2
15
LS1
20
2
T6817
4670C–BCD–09/05
T6817
2. Pin Configuration
Figure 2-1.
Pinning SSO20
GND
DI
CS
CLK
INH
VS
VS
LS3
n.c.
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
VCC
DO
LS1
HS1
LS2
HS2
GND
HS3
GND
Table 2-1.
Pin
1
2
3
4
5
6, 7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
GND
DI
CS
CLK
INH
VS
LS3
n.c.
GND
GND
HS3
GND
HS2
LS2
HS1
LS1
DO
VCC
GND
Function
Ground; reference potential; internal connection to pin 10, 11, 13 and 20; cooling tab
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control
device, DI expects a 16-bit control word with LSB being transferred first
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating
Power supply output stages HS1, HS2 and HS3
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
Not connected
Ground (see pin 1) be consistant
Ground (see pin 1)
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
Ground (see pin 1)
High-side driver output 2 (see pin 12) be consistant
Low-side driver output 2 (see pin 8)
High-side driver output 1 (see pin 12)
Low-side driver output 1 (see pin 8)
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
Logic supply voltage (5V)
Ground (see pin 1)
3
4670C–BCD–09/05
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
CS
Data Transfer Input Data Protocol
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
n.u.
7
n.u.
8
n.u.
9
n.u.
10
n.u.
11
n.u.
12
OLD
13
SCT
14
SI
15
CLK
DO
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
Table 3-1.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Input Data Protocol
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature
shutdown in the output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Not used
Not used
Not used
Not used
Not used
Not used
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short
circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown
delay high/low = 14 ms/3.5 ms
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is
still powered)
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
OLD
SCT
15
SI
4
T6817
4670C–BCD–09/05
T6817
Table 3-2.
Bit
0
Output Data Protocol
Output (Status)
Register
TP
Function
Temperature prewarning: high = warning (overtemperature shut-down,
see remark below)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
Description, see LS1
Description, see HS1
Description, see LS1
Description, see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin 17). High = standby, low = normal operation
Power supply fail: over- or undervoltage at pin VS detected
1
Status LS1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note:
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
Bit 0 to 15 = high: overtemperature shutdown
Table 3-3.
Bit 15 Bit 14
(SI) (SCT)
H
H
Status of the Input Register after Power on Reset
Bit 13
(OLD)
H
Bit 12
n.u.
Bit 11
n.u.
Bit 10
n.u.
Bit 9
n.u.
Bit 8
n.u.
Bit 7
n.u.
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3
(LS2)
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
Bit 0
(SRR)
L
5
4670C–BCD–09/05
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