SY89538L
3.3V, Precision LVPECL and LVDS
Programmable Multiple Output Bank Clock
Synthesizer and Fanout Buffer with Zero Delay
General Description
The SY89538L integrated programmable clock
synthesizer and fanout is part of a precision PLL-
based clock generation family optimized for
enterprise switch, router, and multiprocessor server
applications. This family is ideal for generating
internal system timing requirements up to 750MHz for
multiple ASICs, FPGAs, and NPUs. These devices
integrate the following blocks into a single monolithic
IC:
•
•
•
•
•
•
•
PLL (Phase-Lock-Loop) based synthesizer
Zero-delay MUX and feedback capability
1:4 LVPECL fanout
1:3 LVDS fanout
Clock generator (dividers)
Logic translation (LVPECL, LVDS)
Precision Edge
®
Features
•
Integrated programmable synthesizer with multiple
output dividers, fanout buffers, and clock drivers
•
Zero-delay capability: 29.375MHz to 756MHz
•
Reference clock input: 9.325MHz to 756MHz
•
Input MUX accepts a reference and a crystal
(XTAL) source
– Ideal for reference backup clock source or
system test frequency source
– Patent-pending unique input MUX isolates XTAL
and reference inputs which minimizes crosstalk
•
Guaranteed AC performance:
– Output frequency range: 29.375MHz to 756MHz
– <150ps
PP
total jitter
– <6ps
RMS
cycle-to-cycle jitter (XTAL Input)
– <8ps
PP
deterministic jitter
– <0.7ps
RMS
crosstalk induced jitter
– <75ps output-to-output skew
•
TTL/CMOS-compatible control logic
•
Five-independently programmable output
frequency banks:
– Four differential LVPECL output banks
– One differential LVDS output bank with three
output pairs
•
Output bank synchronization control pin
•
Output enable
•
3.3V ±10% power supply (2.5V output capable)
•
Guaranteed over the industrial temperature range
(-40°C to +85°C)
•
Available in a 64-pin EPAD-TQFP
Five-independently programmable output
banks
This level of integration minimizes additive jitter and
part-to-part
skew
associated
with
discrete
alternatives, resulting in superior system-level timing
with reduced board space and power. For
applications that do not require a zero-delay function,
see the SY89537L.
All support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Applications
•
Enterprise routers, switches, servers and
workstations
•
Parallel processor-based systems
•
Internal system clock generation for ASICs, NPUs
and FPGAs
Markets
•
LAN/WAN
•
Enterprise servers
•
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2008
M9999-010808-E
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89538L
Typical Application
Functional Block Diagram
January 2008
2
M9999-010808-E
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89538L
Ordering Information
(1)
Part Number
SY89538LHY
SY89538LHYTR
(2)
SY89538LHZ
SY89538LHZTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Package
Type
H64-1
H64-1
H64-1
H64-1
Operating
Range
Industrial
Industrial
Commercial
Commercial
Package Marking
SY89538LHY with Pb-Free bar-line indicator
SY89538LHY with Pb-Free bar-line indicator
SY89538LHZ with Pb-Free bar-line indicator
SY89538LHZ with Pb-Free bar-line indicator
Lead
Finish
Matte-Sn
Pb-Free
Matte-Sn
Pb-Free
Matte-Sn
Pb-Free
Matte-Sn
Pb-Free
Pin Configuration
64-Pin EPAD TQFP (H64-1)
January 2008
3
M9999-010808-E
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89538L
Pin Description
Power
Pin Number
1
6, 56
Pin Name
VCCA
VCCD
Pin Function
Analog PLL Power Pin. Connects to “quiet” 3.3V supply. 3.3V power pins must be
connected together on the PCB. Bypass with 0.1µF//0.01µF low ESR capacitors and
place them as close to the VCCA pin as possible.
Digital Logic Core Power Pin. VCCD connects to a 3.3V supply. All power pins must
be connected together on the PCB. Bypass with 0.1µF//0.01µF low ESR capacitors
and place them as close to the VCCD pin as possible.
LVDS and LVPECL Output Driver Power Pins. These outputs can be powered from a
2.5V or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or
2.5V ±5%. All power pins must be connected together on the PCB. Bypass with
0.1µF//0.01µF low ESR capacitor and place them as close to the VCCO pin as
possible.
Analog PLL Ground. Connect to “quiet” ground. GNDA and GND must be connected
together on the PCB.
Ground: GND pins and exposed pad must both be connected to the same ground
plane.
19, 40, 43, 51
VCCO
15
16, 30, 31,
47, 55
GNDA
GND,
Exposed Pad
Control and Configuration
Pin Number
62
Pin Name
LR
Pin Function
Analog Input/Output. Provides the reference voltage for the PLL loop filter and is
used with the LF pin. See “External Loop Filter Considerations” for recommended
loop filter values.
Analog Input/Output. Provides the loop filter node for the PLL. See “External Loop
Filter Considerations” for recommended loop filter values.
TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs.
The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8.
RSEL0 is the LSB bit. See “Reference Input Divider and Zero Delay MUX Divider
Select Table” for proper decoding. The threshold voltage V
TH
= V
CC
/2. Internal 25kΩ
pull-up. The default logic is HIGH.
TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input.
Internal 25kΩ pull-up. The default is logic HIGH, and selects the XTAL input. The
threshold voltage V
TH
= V
CC
/2.
Logic HIGH: XTAL Select
Logic LOW: Reference Input Select
TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL,
DSEL, and LEN are used together to decode the selection and post divider of the
LVDS outputs. Internal 25kΩ pull-up. See “LVDS Output Post-Divider and Frequency
Select Table” for proper decoding. The threshold voltage V
TH
= V
CC
/2. The default
logic is HIGH.
TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as
a frequency select pin. LEN, DSEL, and LSEL are used together to decode the
selection and post divide of the LVDS output bank, see the “LVDS Output Post-
Divider and Frequency Select Table” for proper decoding. Internal 25kΩ pull-up.
When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are
HIGH. The threshold voltage V
TH
= V
CC
/2. The default logic is HIGH.
TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx,
DSEL and PENx are used together to decode the selection and post divider of the
PECL outputs. PSELx pins include an internal 25kΩ pull-up. The threshold voltage
V
TH
= V
CC
/2. See "LVPECL Output Post-Divider and Frequency Select Table” for
proper decoding.
63
2, 7
LF
RSEL1, RSEL0
10
INSEL
36
LSEL
37
LEN
23
25
57
59
PSEL0
PSEL1
PSEL2
PSEL3
January 2008
4
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hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89538L
Pin Description
Control and Configuration
(continued)
Pin Number
24
26
58
60
46
Pin Name
PEN0
PEN1
PEN2
PEN3
SYNC
Pin Function
TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and
as a frequency select pins. PENx, PSELx, and DSEL are used together; see the
“LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
PENx contains internal 25kΩ pull-up. When disabled, PECL0-PECL3 outputs are a
logic LOW. The threshold voltage V
TH
= V
CC
/2.
TTL/CMOS Output Bank Synchronization Control. Internal 25kΩ pull-up. The default
state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are
synchronized when the SYNC control pin is toggled with a HIGH-LOW-HIGH
transition. See “Synchronization” section for details. The threshold voltage V
TH
=
V
CC
/2.
TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay
function). Internal 25kΩ pull-up. The threshold voltage V
TH
= V
CC
/2. Default is logic
HIGH, and selects internal feedback.
Logic HIGH: Internal feedback (from the Programmable Divider)
Logic Low: External feedback (from the FBIN inputs)
TTL/CMOS Programmable Divider-Select Control. Internal 25kΩ pull-down. Default is
logic LOW. The threshold voltage V
TH
= V
CC
/2. See “Programmable-Divider Select Table”
for proper decoding.
TTL/CMOS Programmable Divider-Select Control. Internal 25kΩ pull-up. Default is logic
HIGH. The threshold voltage V
TH
= V
CC
/2. See “Programmable-Divider Select Table” for
proper decoding.
TTL/CMOS Pre-Divider Select Input. Internal 25kΩ pull-up. This two-bit input divider
scales the VCO/2 frequency. See “Pre-Divider Frequency Select Table” for proper
decoding. The threshold voltage V
TH
= V
CC
/2.
TTL/CMOS Post-Divider Option Control. Internal 25kΩ pull-up. Default is logic HIGH.
The threshold voltage V
TH
= V
CC
/2.
Logic HIGH: All LVPECL and LVDS outputs operate with their respective output
frequency control (PSELx, PENx, LSEL, LEN).
Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL
through a /1, /4, and /16 Post-Divider.
See “LVPECL and LVDS Output Post-Divider and Frequency Select Table” for proper
decoding.
5
FBSEL
28
33
35
27
29
34
13, 14
PD_4
PD_2
PD_0
PD_5
PD_3
PD_1
PDSEL1,
PDSEL0
DSEL
22
January 2008
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or (408) 955-1690
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