82V3285DQ8 datasheet, PDF - EEWORLD Datasheet

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82V3285DQ8: DescriptionTelecom Circuit, 1-Func, PQFP100, TQFP-100; CategoryWireless rf/communication Telecom circuit; File Size1MB，143 Pages; ManufacturerIDT (Integrated Device Technology)

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82V3285DQ8 Overview

Telecom Circuit, 1-Func, PQFP100, TQFP-100

82V3285DQ8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
package instruction	TQFP-100
Reach Compliance Code	not_compliant
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Base Number Matches	1

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WAN PLL

IDT82V3285

Version -

March 02, 2009

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18

RESET ........................................................................................................................................................................................................... 18

MASTER CLOCK .......................................................................................................................................................................................... 18

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 19

3.3.1 Input Clocks .................................................................................................................................................................................... 19

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21

3.5.1 Activity Monitoring ......................................................................................................................................................................... 21

3.5.2 Frequency Monitoring ................................................................................................................................................................... 22

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23

3.6.2 Forced Selection ............................................................................................................................................................................ 24

3.6.3 Automatic Selection ....................................................................................................................................................................... 24

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25

3.7.1.1 Fast Loss .......................................................................................................................................................................... 25

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25

3.7.2 Locking Status ............................................................................................................................................................................... 25

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27

3.8.1 Input Clock Validity ........................................................................................................................................................................ 27

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27

3.8.2.1 Revertive Switch ............................................................................................................................................................... 27

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32

3.10.1.3 Locked Mode .................................................................................................................................................................... 32

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32

3.1

3.2

3.3

Table of Contents

March 02,

2009

IDT82V3285

WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

4 TYPICAL APPLICATION ................................................................................................................................................. 44

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 44

EPROM MODE .............................................................................................................................................................................................. 46

MULTIPLEXED MODE .................................................................................................................................................................................. 47

INTEL MODE ................................................................................................................................................................................................. 49

MOTOROLA MODE ...................................................................................................................................................................................... 51

SERIAL MODE .............................................................................................................................................................................................. 53

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32

3.10.1.5 Holdover Mode ................................................................................................................................................................. 32

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33

3.10.1.5.4 Manual ........................................................................................................................................................... 33

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33

3.10.2.2 Locked Mode .................................................................................................................................................................... 33

3.10.2.3 Holdover Mode ................................................................................................................................................................. 33

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35

3.11.1 PFD Output Limit ............................................................................................................................................................................ 35

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35

3.11.5.1 T0 Path ............................................................................................................................................................................. 35

3.11.5.2 T4 Path ............................................................................................................................................................................. 36

T0 / T4 APLL ................................................................................................................................................................................................. 37

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37

3.13.1 Output Clocks ................................................................................................................................................................................. 37

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 41

INTERRUPT SUMMARY ............................................................................................................................................................................... 42

T0 AND T4 SUMMARY ................................................................................................................................................................................. 42

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 45

6 JTAG ................................................................................................................................................................................ 55

7 PROGRAMMING INFORMATION .................................................................................................................................... 56

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 56

REGISTER DESCRIPTION ........................................................................................................................................................................... 61

7.2.1 Global Control Registers ............................................................................................................................................................... 61

7.2.2 Interrupt Registers ......................................................................................................................................................................... 70

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 74

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 85

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 96

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103

7.2.8 Output Configuration Registers .................................................................................................................................................. 117

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 124

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 126

JUNCTION TEMPERATURE ...................................................................................................................................................................... 127

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 127

8 THERMAL MANAGEMENT ........................................................................................................................................... 127

8.1

8.2

Table of Contents

March 02, 2009

IDT82V3285

WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 128

9.1

9.2

9.3

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 128

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 128

I/O SPECIFICATIONS ................................................................................................................................................................................. 129

9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 129

9.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 130

9.3.2.1 PECL Input / Output Port ................................................................................................................................................ 130

9.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 132

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 133

OUTPUT WANDER GENERATION ............................................................................................................................................................ 136

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 137

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 138

8.3

HEATSINK EVALUATION .......................................................................................................................................................................... 127

ORDERING INFORMATION .......................................................................................................................................... 143

9.4

9.5

9.6

9.7

Table of Contents

March 02, 2009

82V3285DQ8 Related Products

	82V3285DQ8	82V3285DQ	82V3285DQG8	82V3285DQG
Description	Telecom Circuit, 1-Func, PQFP100, TQFP-100	Telecom Circuit, 1-Func, PQFP100, TQFP-100	Telecom Circuit, 1-Func, PQFP100, GREEN, TQFP-100	Telecom Circuit, 1-Func, PQFP100, GREEN, TQFP-100
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	TQFP-100	TQFP-100	GREEN, TQFP-100	LFQFP,
Reach Compliance Code	not_compliant	not_compliant	compliant	unknown
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
Number of functions	1	1	1	1
Number of terminals	100	100	100	100
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	LFQFP	QFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	QUAD	QUAD	QUAD
Base Number Matches	1	1	1	1
Is it lead-free?	Contains lead	Contains lead	Lead free	-
Is it Rohs certified?	incompatible	incompatible	conform to	-
JESD-609 code	e0	e0	e3	-
Humidity sensitivity level	3	3	3	-
Peak Reflow Temperature (Celsius)	225	225	260	-
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn) - annealed	-
Maximum time at peak reflow temperature	30	30	30	-

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