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MC74VHC1G04DFT4

Description
AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5
Categorylogic    logic   
File Size148KB,4 Pages
ManufacturerLRC
Websitehttp://www.lrc.cn
Download Datasheet Parametric Compare View All

MC74VHC1G04DFT4 Overview

AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5

MC74VHC1G04DFT4 Parametric

Parameter NameAttribute value
MakerLRC
package instructionTSSOP, TSSOP5/6,.08
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G5
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.008 A
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP5/6,.08
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply2/5.5 V
Prop。Delay @ Nom-Su10 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
LESHAN RADIO COMPANY, LTD.
Inverter
MC74VHC1G04
The MC74VHC1G04 is an advanced high speed CMOS inverter fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The MC74VHC1G04 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G04 to be used to interface 5 V circuits to 3 V circuits.
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 105; Equivalent Gates = 26
MARKING DIAGRAMS
5
4
1
2
3
V5
d
SC–70/SC–88A/SOT–353
DF SUFFIX
CASE 419A
Pin 1
d = Date Code
5
4
Figure 1. Pinout
(Top View)
1
2
3
V5
d
Figure 2. Logic Symbol
Pin 1
d = Date Code
SOT–23/TSOP–5/SC–59
DT SUFFIX
CASE 483
FUNCTION TABLE
PIN ASSIGNMENT
1
2
3
4
5
NC
IN A
GND
OUT Y
V
CC
Inputs
A
L
H
Output
Y
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
VH4–1/4

MC74VHC1G04DFT4 Related Products

MC74VHC1G04DFT4 MC74VHC1G04DFT2 MC74VHC1G04DTT3 MC74VHC1G04
Description AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5 AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5 AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5 AHC/VHC SERIES, 1-INPUT INVERT GATE, PDSO5
Number of terminals 5 5 5 5
Maximum operating temperature 125 °C 125 °C 125 °C 125 Cel
Minimum operating temperature -55 °C -55 °C -55 °C -55 Cel
surface mount YES YES YES Yes
Temperature level MILITARY MILITARY MILITARY MILITARY
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL pair
Maker LRC LRC LRC -
package instruction TSSOP, TSSOP5/6,.08 TSSOP, TSSOP5/6,.08 TSOP, TSOP5/6,.11,37 -
Reach Compliance Code unknow unknow unknow -
JESD-30 code R-PDSO-G5 R-PDSO-G5 R-PDSO-G5 -
Load capacitance (CL) 50 pF 50 pF 50 pF -
Logic integrated circuit type INVERTER INVERTER INVERTER -
MaximumI(ol) 0.008 A 0.008 A 0.008 A -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code TSSOP TSSOP TSOP -
Encapsulate equivalent code TSSOP5/6,.08 TSSOP5/6,.08 TSOP5/6,.11,37 -
Package shape RECTANGULAR RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE -
method of packing TAPE AND REEL TAPE AND REEL TAPE AND REEL -
power supply 2/5.5 V 2/5.5 V 2/5.5 V -
Prop。Delay @ Nom-Su 10 ns 10 ns 10 ns -
Certification status Not Qualified Not Qualified Not Qualified -
Schmitt trigger NO NO NO -
technology CMOS CMOS CMOS -
Terminal pitch 0.635 mm 0.635 mm 0.95 mm -
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