Data Sheet No.PD60270
IRS2004(S)PbF
HALF-BRIDGE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
Fully operational to +200 V
•
Tolerant to negative transient voltage, dV/dt
immune
•
Gate drive supply range from 10 V to 20 V
•
Undervoltage lockout
•
3.3 V, 5 V, and 15 V input logic compatible
•
Cross-conduction prevention logic
•
Internally set deadtime
•
High-side output in phase with input
•
Shutdown input turns off both channels
•
Matched propagation delay for both channels
•
RoHS compliant
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Deadtime (typ.)
200 V max.
130 mA/270 mA
10 V - 20 V
680 ns/150 ns
520 ns
Packages
Description
The IRS2004 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high- and low-
side referenced output channels. Proprietary HVIC and
8 Lead SOIC
8 Lead PDIP
latch immune CMOS technologies enable ruggedized
IRS2004S
IRS2004
monolithic construction. The logic input is compatible
with standard CMOS or LSTTL output, down to 3.3 V
logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates from 10 V to 200 V.
Typical Connection
up to 200 V
V
CC
V
CC
IN
SD
V
B
HO
V
S
LO
TO
LOAD
IN
SD
COM
(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IRS2004(S) PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
s
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High-side floating absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage (IN &
SD
)
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25
°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 lead PDIP)
(8 lead SOIC)
(8 lead PDIP)
(8 lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
—
—
—
—
—
—
-55
—
Max.
225
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The
input/output
logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at a 15 V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage (IN &
SD
)
Ambient temperature
Min.
V
S
+ 10
Note 2
V
S
10
0
0
-40
Max.
V
S
+ 20
200
V
B
20
V
CC
V
CC
125
Units
V
°C
Note 1: Logic operational for V
S
of -5 V to +200 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
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2
IRS2004(S) PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, C
L
= 1000 pF and T
A
= 25
°C
unless otherwise specified.
Symbol
ton
toff
tsd
tr
tf
DT
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Shutdown propagation delay
Turn-on rise time
Turn-off fall time
Deadtime, LS turn-off to HS turn-on &
HS turn-on to LS turn-off
Delay matching, HS & LS turn-on/off
Min. Typ. Max. Units Test Conditions
—
—
—
—
—
400
—
680
150
160
70
35
520
—
820
220
220
170
90
650
60
ns
V
S
= 0 V
V
S
= 200 V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V and T
A
= 25
°C
unless otherwise specified. The V
IN
, V
TH,
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
SD,TH+
V
SD,TH-
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” (HO) & Logic “0” (LO) input voltage
Logic “0” (HO) & Logic “1” (LO) input voltage
SD input positive going threshold
SD input negative going threshold
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
supply undervoltage positive going
threshold
V
CC
supply undervoltage negative going
threshold
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.5
—
2.5
—
—
—
—
—
—
—
—
8
7.4
130
270
—
—
—
—
0.05
0.02
—
30
150
3
—
8.9
8.2
290
600
—
0.8
—
0.8
0.2
0.1
50
55
270
10
5
9.8
V
9
—
mA
—
V
O
= 0 V
PW
≤
10
µs
V
O
= 15 V
PW
≤
10
µs
µA
V
I
O
= 2 mA
V
B
= V
S
= 200 V
V
IN
= 0 V or 5 V
V
IN
= 5 V
V
IN
= 0 V
V
CC
= 10 V to 20 V
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3
IRS2004(S) PbF
Functional Block Diagram
VB
HV
LEVEL
SHIFT
Q
PULSE
FILTER
R
S
VS
HO
IN
PULSE
GEN
DEAD TIME &
SHOOT-THROUGH
PREVENTION
UV
DETECT
VCC
SD
LO
COM
Lead Definitions
Symbol Description
IN
Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
Logic input for shutdown
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
Low-side return
SD
V
B
HO
V
S
V
CC
LO
COM
Lead Assignments
1
2
3
4
VCC
IN
SD
COM
VB
HO
VS
LO
8
7
6
5
1
2
3
4
VCC
IN
SD
COM
VB
HO
VS
LO
8
7
6
5
8 Lead PDIP
8 Lead SOIC
IRS2004PbF
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IRS2004SPbF
4
IRS2004(S) PbF
IN
IN
(LO)
50%
50%
SD
IN
(HO)
ton
tr
90%
toff
90%
tf
HO
LO
LO
HO
Figure 1. Input/Output Timing Diagram
10%
10%
Figure 2. Switching Time Waveform Definitions
50%
50%
IN
SD
50%
90%
tsd
HO
DT
10%
DT
HO
LO
90%
LO
90%
10%
Figure 3. Shutdown Waveform Definitions
Figure 4. Deadtime Waveform Definitions
IN
(LO)
50%
50%
IN
(HO)
LO
HO
10%
MT
90%
MT
LO
HO
Figure 5. Delay Matching Waveform Definitions
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