3.3 VOLT CMOS SyncBiFIFO
TM
64 x 36 x 2
FEATURES:
•
•
•
•
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•
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•
•
•
IDT72V3612
•
•
•
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•
Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
Supports clock frequencies up to 83 MHz
Fast access times of 8ns
Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
Mailbox bypass Register for each FIFO
Programmable Almost-Full and Almost-Empty Flags
Microprocessor interface control logic
EFA
,
FFA
,
AEA
, and
AFA
flags synchronized by CLKA
EFB
,
FFB
,
AEB
, and
AFB
flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723612
°
°
Industrial temperature range (–40°C +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V3612 is a pin and functionally compatible version of the
IDT723612, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithic high-speed, low-power CMOS bi-
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Mail 1
Register
Parity
Gen/Check
MBF1
PEFB
PGB
Parity
Generation
Input
Register
RST
ODD/
EVEN
Device
Control
RAM
ARRAY
64 x 36
Output
Register
36
Write
Pointer
FFA
AFA
36
Read
Pointer
EFB
AEB
Status Flag
Logic
FIFO1
Programmable Flag
Offset Register
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
36
FS0
FS1
A
0
- A
35
EFA
AEA
B
0
- B
36
FFB
AFB
Parity
Generation
Output
Register
RAM
ARRAY
64 x 36
PGA
Parity
Gen/Check
Mail 2
Register
CLKB
CSB
W/RB
ENB
MBB
4659 drw 01
PEFA
MBF2
Input
Register
Port-B
Control
Logic
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2009
DSC-4659/3
1
©2009
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
directional clocked FIFO memory. It supports clock frequencies up to 83 MHz
and has read access times as fast as 8ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (Almost-Full and Almost-Empty) to
indicate when a selected number of words is stored in memory. Communication
between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
can be used in parallel to create wider data paths.
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a port clock by enable signals. The clocks for each port
are independent of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi-directional interface
between microprocessors and/or buses with synchronous control.
The Full Flag (FFA,
FFB)
and Almost-Full (AFA,
AFB)
flag of a FIFO are
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (EFA,
EFB)
and Almost-Empty (AEA,
AEB)
flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT72V3612 is characterized for operation from 0°C to 70°C. Industrial
temperature range (–40°C to +85°C) is available by special order. This device
is fabricated using IDT's high speed, submicron CMOS technology.
V
CC
A
24
A
25
A
26
GND
A
27
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
V
CC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
GND
AEA
EFA
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
GND
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
GND
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
AFB
PIN CONFIGURATIONS
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
AEB
EFB
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
NOTES:
1.
Electrical pin 1 in center of beveled edge.
2. NC - No internal connection.
3. Uses Yamaichi socket IC51-1324-828.
4659 drw 02
PQFP
(3)
(PQ132-1, order code: PQF)
TOP VIEW
2
FEBRUARY 12, 2009
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
32
A
33
A
34
A
35
GND
B
35
B
34
B
33
B
32
B
31
B
30
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
B
23
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
EFA
AEA
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EFB
AEB
AFB
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF
2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF
1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
TQFP (PN120-1, order code: PF)
TOP VIEW
NOTES:
1. Pin 1 identifier in corner.
2. NC - No internal connection.
4659 drw 03
3
FEBRUARY 12, 2009
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
AEA
AEB
AFA
AFB
B0-B35
CLKA
Name
Port A Data
Port A Almost-Empty
Flag
Port B Almost-Empty
Flag
Port A Almost-Full
Flag
Port B Almost-Full
Flag
Port B Data.
Port A Clock
I/O
I/O
O
(Port A)
O
(PortB)
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
the FIFO2 is less than or equal to the value in the offset register, X.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
FIFO1 is less than or equal to the value in the offset register, X.
Description
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
I/O
I
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB.
EFA, FFA, AFA,
and
AEA
are synchronized to the LOW-to-
HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA.
EFB, FFB, AFB,
and
AEB
are synchronized to the LOW-to-
HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
The B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
CLKB
Port B Clock
I
CSA
CSB
EFA
Port A Chip Select
Port B Chip Select
Port A Empty Flag
I
I
O
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
is LOW, FIFO2 is empty,
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register
when
EFA
is HIGH.
EFA
is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
O
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
is LOW, the FIFO1 is
(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when
EFB
is HIGH.
EFB
is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
EFB
Port B Empty Flag
ENA
ENB
FFA
Port A Enable
Port B Enable
Port A Full Flag
O
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is LOW, FIFO1 is full,
(Port A) and writes to its memory are disabled.
FFA
is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
O
FFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
FFB
is LOW, FIFO2 is full,
(Port B) and writes to its memory are disabled.
FFB
is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
I
I
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag.
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output,
and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects FIFO1 output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while
MBF1
is set LOW.
MBF1
is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and MBB is HIGH.
MBF1
is set HIGH
when the device is reset.
FFB
Port B Full Flag
FS1, FS0
MBA
Flag Offset Selects
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register Flag
MBB
I
MBF1
O
4
FEBRUARY 12, 2009
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
MBF2
Name
Mail2 Register Flag
I/O
O
Description
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while
MBF2
is set LOW.
MBF2
is set HIGH by a LOW-to-
HIGH transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2
is set HIGH
when the device is reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW. Bytes are organized as
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having W/RA LOW, MBA HIGH, and PGA HIGH, the
PEFA
flag is forced HIGH regardless of the
A0-A35 inputs.
When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW. Bytes are organized as
B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
W/RB LOW, MBB HIGH, and PGB HIGH, the
PEFB
flag is forced HIGH regardless of the state of
the B0-B35 inputs.
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,
and B27-B35. The generated parity bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of
CLKB must occur while
RST
is LOW. This sets the
AFA, AFB, MBF1,
and
MBF2
flags HIGH and
the
EFA, EFB, AEA, AEB, FFA,
and
FFB
flags LOW. The LOW-to-HIGH transition of
RST
latches
the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-
HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is
HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-
HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is
HIGH.
ODD/
EVEN
PEFA
Odd/Even Parity
Select
Port A Parity Error
Flag
I
O
(Port A)
PEFB
Port B Parity Error
Flag
O
(Port B)
PGA
Port A Parity
Generation
Port B Parity
Generation
Reset
I
PGB
I
RST
I
W/RA
Port A Write/Read
Select
Port B Write/Read
Select
I
W/RB
I
5
FEBRUARY 12, 2009
Analogue and Mixed Signal
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