72V3612L15PQFG datasheet, PDF - EEWORLD Datasheet

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72V3612L15PQFG: DescriptionBi-Directional FIFO, 64X36, 10ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132; Categorystorage storage; File Size240KB，25 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72V3612L15PQFG Overview

Bi-Directional FIFO, 64X36, 10ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132

72V3612L15PQFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	GREEN, PLASTIC, QFP-132
Contacts	132
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	10 ns
Other features	MAIL BOX BYPASS REGISTER; PARITY GENERATOR/CHECKER
Maximum clock frequency (fCLK)	66.7 MHz
period time	15 ns
JESD-30 code	S-PQFP-G132
JESD-609 code	e3
length	24.13 mm
memory density	2304 bit
Memory IC Type	BI-DIRECTIONAL FIFO
memory width	36
Number of functions	1
Number of terminals	132
word count	64 words
character code	64
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64X36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	SPQFP132,1.1SQ
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.0005 A
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.13 mm

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3.3 VOLT CMOS SyncBiFIFO

64 x 36 x 2

FEATURES:

•

IDT72V3612

•

Two independent clocked FIFOs (64 x 36 storage capacity each)

buffering data in opposite directions

Supports clock frequencies up to 83 MHz

Fast access times of 8ns

Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

Mailbox bypass Register for each FIFO

Programmable Almost-Full and Almost-Empty Flags

Microprocessor interface control logic

EFA

FFA

AEA

, and

AFA

flags synchronized by CLKA

EFB

FFB

AEB

, and

AFB

flags synchronized by CLKB

Passive parity checking on each port

Parity generation can be selected for each port

Available in 132-pin plastic quad flat package (PQF), or space

saving 120-pin thin quad flat package (TQFP)

Pin and functionally compatible version of the 5V operating

IDT723612

Industrial temperature range (–40°C +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

The IDT72V3612 is a pin and functionally compatible version of the

IDT723612, designed to run off a 3.3V supply for exceptionally low-power

consumption. This device is a monolithic high-speed, low-power CMOS bi-

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

Mail 1

Parity

Gen/Check

MBF1

PEFB

PGB

Parity

Generation

Input

RST

ODD/

EVEN

Device

Control

RAM

ARRAY

64 x 36

Output

Write

Pointer

FFA

AFA

Read

Pointer

EFB

AEB

Status Flag

Logic

FIFO1

Programmable Flag

Offset Register

FIFO2

Status Flag

Logic

Read

Pointer

Write

Pointer

FS0

FS1

- A

EFA

AEA

- B

FFB

AFB

Parity

Generation

Output

RAM

ARRAY

64 x 36

PGA

Parity

Gen/Check

Mail 2

CLKB

CSB

W/RB

ENB

MBB

4659 drw 01

PEFA

MBF2

Input

Port-B

Control

Logic

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

FEBRUARY 2009

DSC-4659/3

IDT72V3612 3.3V, CMOS SyncBiFIFO

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol

MBF2

Name

Mail2 Register Flag

I/O

Description

MBF2

is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.

Writes to the mail2 register are inhibited while

MBF2

is set LOW.

MBF2

is set HIGH by a LOW-to-

HIGH transition of CLKA when a port A read is selected and MBA is HIGH.

MBF2

is set HIGH

when the device is reset.

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when

ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity

generation is enabled for a read operation.

When any byte applied to terminals A0-A35 fails parity,

PEFA

is LOW. Bytes are organized as

A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the

parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The

parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if

parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by

having W/RA LOW, MBA HIGH, and PGA HIGH, the

PEFA

flag is forced HIGH regardless of the

A0-A35 inputs.

When any byte applied to terminals B0-B35 fails parity,

PEFB

is LOW. Bytes are organized as

B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity

bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees

used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having

W/RB LOW, MBB HIGH, and PGB HIGH, the

PEFB

flag is forced HIGH regardless of the state of

the B0-B35 inputs.

Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,

and A27-A35. The generated parity bits are output in the most significant bit of each byte.

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,

and B27-B35. The generated parity bits are output in the most significant bit of each byte.

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while

RST

is LOW. This sets the

AFA, AFB, MBF1,

and

MBF2

flags HIGH and

the

EFA, EFB, AEA, AEB, FFA,

and

FFB

flags LOW. The LOW-to-HIGH transition of

RST

latches

the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset.

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-

HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is

HIGH.

A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-

HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is

HIGH.

ODD/

EVEN

PEFA

Odd/Even Parity

Select

Port A Parity Error

Flag

(Port A)

PEFB

Port B Parity Error

Flag

(Port B)

PGA

Port A Parity

Generation

Port B Parity

Generation

Reset

PGB

RST

W/RA

Port A Write/Read

Select

Port B Write/Read

Select

W/RB

FEBRUARY 12, 2009

72V3612L15PQFG Related Products

	72V3612L15PQFG	72V3612L20PFG	72V3612L12PQFG	72V3612L20PQFG
Description	Bi-Directional FIFO, 64X36, 10ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132	Bi-Directional FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP120, GREEN, TQFP-120	Bi-Directional FIFO, 64X36, 8ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132	Bi-Directional FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
Is it lead-free?	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP
package instruction	GREEN, PLASTIC, QFP-132	LFQFP, QFP120,.63SQ,16	GREEN, PLASTIC, QFP-132	GREEN, PLASTIC, QFP-132
Contacts	132	120	132	132
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
Maximum access time	10 ns	12 ns	8 ns	12 ns
Other features	MAIL BOX BYPASS REGISTER; PARITY GENERATOR/CHECKER	MAIL BOX BYPASS REGISTER; PARITY GENERATOR/CHECKER	MAIL BOX BYPASS REGISTER; PARITY GENERATOR/CHECKER	MAIL BOX BYPASS REGISTER; PARITY GENERATOR/CHECKER
Maximum clock frequency (fCLK)	66.7 MHz	50 MHz	83 MHz	50 MHz
period time	15 ns	20 ns	12 ns	20 ns
JESD-30 code	S-PQFP-G132	S-PQFP-G120	S-PQFP-G132	S-PQFP-G132
JESD-609 code	e3	e3	e3	e3
length	24.13 mm	14 mm	24.13 mm	24.13 mm
memory density	2304 bit	2304 bit	2304 bit	2304 bit
Memory IC Type	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO
memory width	36	36	36	36
Number of functions	1	1	1	1
Number of terminals	132	120	132	132
word count	64 words	64 words	64 words	64 words
character code	64	64	64	64
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	64X36	64X36	64X36	64X36
Exportable	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	LFQFP	QFP	QFP
Encapsulate equivalent code	SPQFP132,1.1SQ	QFP120,.63SQ,16	SPQFP132,1.1SQ	SPQFP132,1.1SQ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	1.6 mm	4.572 mm	4.572 mm
Maximum standby current	0.0005 A	0.0005 A	0.0005 A	0.0005 A
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	Matte Tin (Sn) - annealed	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.4 mm	0.635 mm	0.635 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	24.13 mm	14 mm	24.13 mm	24.13 mm
Base Number Matches	-	1	1	1

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