xr
NOVEMBER 2006
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. 1.0.0
XRK39653 GENERAL DESCRIPTION
The XRK39653 is a low voltage high performance PLL
based zero delay buffer/clock generator designed for high
speed clock distribution applications. It provides 9 low
skew, low jitter outputs ideal for networking, computing and
telecom applications.
The PLL based design allows the 9 outputs (8 clock outputs
and 1 feedback output) to be phase aligned to the input ref-
erence clock. The outputs source LVCMOS compatible lev-
els and can drive 50Ω transmission lines. If series
termination is used, each output can drive up to 2 lines pro-
viding effectively a fanout of 1:16. The XRK39653’s refer-
ence input accepts a LVPECL clock source.
For normal operation (PLL used to source the outputs), the
feedback output (QFB) is connected to the feedback input
(FB_IN). The VCO range of operation is 200 to 500MHz.
This means that the input/output ranges are determined by
the divider setting. If ÷4 is used, the input/output range is 50
to 125MHz (high range), if ÷8 is used the input/output range
is 25 to 62.5MHz (low range).
For testing purposes two PLL bypass modes are provided.
The first simply replaces the PLL output with the reference
clock (PLL_EN=0, BYPASS=1). The dividers are still in
use. The second is a full bypass mode that has the PLL
and divider operation removed (BYPASS=0). In this mode
the reference clock directly sources the outputs drivers.
FEATURES
•
8 LVCMOS Clock Outputs
•
1 Feedback Output
•
LVPECL reference clock input
•
25-125 MHz input/output frequency range
■
■
Input/Output range (
÷4): 50-125MHz
Input/Output range (
÷8): 25-62.5MHz
•
150ps max output to output skew
•
Two bypass test mode options
•
Fully Integrated PLL
•
3.3V Operation
•
Pin compatible with MPC9653
•
Industrial temp range:
-40°C to +85°C
•
32-Lead TQFP Packaging
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRK39653
VDD
QFB
0
0
1
÷2
1
÷4
1
Q0
0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PECL
PECL
FB_IN
Ref
PLL
VDD
FB
PLL_EN
VCO_SEL
BYPASS
OE
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
XRK39653CQ
XRK39653IQ
P
ACKAGE
T
YPE
32-Lead TQFP
32-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
F
IGURE
2. P
IN
O
UT OF THE
XRK39653
VCO_SEL
BYPASS
PLL_EN
GND
32
AVDD
FB_IN
NC
NC
NC
NC
AGND
PECL
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
22
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
GND
VDD
QFB
Q0
XRK39653
21
20
19
18
17
10
11
12
13
14
15
16
PECL
GND
VDD
VDD
OE
Q7
Q6
2
Q5
rx
REV. 1.0.0
rx
REV. 1.0.0
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PIN DESCRIPTIONS
N
UMBER
1
2
N
AME
AVDD
FB_IN
NC
AGND
PECL
PECL
OE
VDD
Q[7:0]
Power
Input
Input
Input
Power
Output
pull-down
PLL ground
LVPECL - pos differential reference clock
LVPECL - neg differential reference clock
Output enable/disable and device reset
Power supply
Clock outputs
Power
Input
pull-up
T
YPE
Power supply for PLL
External PLL feedback clock input
D
ESCRIPTION
3, 4, 5, 6
7
8
9
10
11,15, 19,
23, 27,
12, 14, 16,
18, 20, 22,
24, 26
13, 17, 21,
25, 29
28
30
31
32
GND
QFB
PLL_EN
BYPASS
VCO_SEL
Power
Output
Input
Input
Input
pull-up
pull-up
pull-up
Ground
Feedback output for PLL
PLL enable/disable select
PLL and output divider bypass select
VCO divider select
T
ABLE
1: CONTROL INPUT FUNCTION TABLE
Pin Name
VCO_SEL
PLL_EN
0
System Divide = 4 of VCO output
PLL is bypassed and disabled. The PECL
clock reference source drives the outputs
through the divider blocks
Complete bypass of the PLL and divider
blocks. PECL reference clocks the outputs.
Outputs enabled
1
System Divide = 8 of VCO output
PLL enabled. Normal operation. VCO out-
put drives the outputs through the divider
blocks
Normal operation. Dividers selected.
Outputs tri-stated and device reset. VCO
running at minimum frequency
Default
1
1
BYPASS
OE
1
0
3
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
DC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
S
YMBOL
V
CMRa
V
PP
V
IH
V
IL
V
OH
V
OL
C
HARACTERISTICS
PECL Clock inputs common mode range
PECL Clock peak-to-peak input voltage
Input voltage high
Input voltage low
Output High Voltage
a
Output Low Voltage
a
2.4
0.55
0.30
14-17
+200
5.0
10.0
10.0
V
CC
÷2
M
IN
1.0
300
2.0
T
YP
M
AX
V
DD
-0.6
1000
V
DD
+0.3
0.8
U
NIT
V
mV
V
V
V
V
V
Ω
μΑ
mA
mA
V
LVPECL
LVPECL
LVCMOS
LVCMOS
I
OH
=-24mA
I
OL
=24mA
I
OL
=12mA
Z
OUT
I
IN
I
CC_PLL
I
CCQ
V
TT
Output Impedance
Input leakage current
Maximum PLL supply current
Maximum Quiescent supply current
Output Termination Voltage
V
IN
=V
DD
or V
IN
=GND
AV
DD
pin
All V
DD
pins, OE=1
a.
VCMR is the cross point of the differential input signal.
.
AC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
a
S
YMBOL
f
VCO
f
ref
VCO Frequency
Input Reference Frequency
÷4 feedback
÷8 feedback
PLL Bypass
÷4 feedback
÷8 feedback
P
ARAMETER
M
IN
200
50
25
0
50
25
450
1.2
2
-75
125
T
YP
M
AX
500
125
62.5
200
125
62.5
1000
V
DD
-0.75
U
NIT
MHz
MHz
PLL locked
PLL locked
bypass mode
PLL locked
PLL locked
LVPECL
LVPECL
C
ONDITION
f
MAX
V
PP
V
CMR
t
PW Min
t
SPO
t
PD
Max Output Frequency
MHz
PECL Clock peak-to-peak input voltage
PECL input Common Mode range
Input Reference Clock Minimum Pulse Width
Propagation Delay - Static Phase Offset (PECL
to FB_IN)
Propagation Delay - PLL Bypassed
Bypass mode 1 (BYPASS = 0)
Bypass mode 2, (BYPASS = 1, PLL_EN = 0)
Output-to-Output Skew
Part to Part Skew (bypass PLL & divider)
Cycle-to-Cycle Jitter
mV
V
ns
ps
1.2
3.0
3.3
7.0
150
1.5
100
ns
ns
ps
ns
ps
BYPASS=0
t
skew(O)
t
skew(PP)
t
JIT(CC)
4
rx
REV. 1.0.0
C
ONDITION
PLL locked
rx
REV. 1.0.0
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
AC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
a
S
YMBOL
t
JIT(PER)
t
JIT(I/O)
BW
P
ARAMETER
M
IN
T
YP
M
AX
100
25
÷4 feedback
÷8 feedback
45
50
0.8 - 4
0.5 - 1.3
55
10.0
100
1000
7
6
U
NIT
ps
ps
MHz
MHz
%
ms
ps
ns
ns
0.55 to 2.4V
PLL locked
C
ONDITION
Period Jitter
I/O Phase Jitter (RMS)
PLL bandwidth
DC
t
LOCK
t
or
/t
of
t
PLZ,HZ
t
PHZ,LZ
Output duty cycle
Maximum PLL Lock Time
Output Rise/Fall time
Output Disable Time
Output Enable Time
a.
AC characteristics apply for parallel output termination of 50Ω to V
TT
.
MAXIMUM RATINGS
a
S
YMBOL
V
DD
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
-65
CHARACTERISTICS
M
IN
-0.3
-0.3
-0.3
M
AX
3.9
V
DD
+0.3
V
DD
+0.3
+20
+50
125
U
NIT
V
V
V
mA
mA
°C
C
ONDITION
a.
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
S
YMBOL
V
TT
MM
HBM
LU
C
IN
C
HARACTERISTICS
Output termination voltage
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up immunity
Input Capacitance
200
2000
200
4.0
M
IN
T
YP
V
CC
÷2
M
AX
U
NIT
V
V
V
mA
pF
Inputs
C
ONDITION
5
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