3293-11 datasheet, PDF - EEWORLD Datasheet

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3293-11: DescriptionPhase Locked Loop, CMOS, PDSO20, 0.65 MM PITCH, MO-153AC, TSSOP-20; CategoryAnalog mixed-signal IC The signal circuit; File Size205KB，13 Pages; ManufacturerpSemi (peregrine semiconductor); Websitehttp://www.psemi.com/

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3293-11 Overview

Phase Locked Loop, CMOS, PDSO20, 0.65 MM PITCH, MO-153AC, TSSOP-20

3293-11 Parametric

Parameter Name	Attribute value
Maker	pSemi (peregrine semiconductor)
Parts packaging code	TSSOP
package instruction	0.65 MM PITCH, MO-153AC, TSSOP-20
Contacts	20
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-PDSO-G20
length	6.5 mm
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
Base Number Matches	1

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Product Specification

PE3293

Product Description

The PE3293 is a dual fractional-N phase-lock loop (PLL) IC

designed for frequency synthesis, developed on Peregrine’s

UltraCMOS™ process technology. Each PLL includes a

prescaler, phase detector, charge pump and on-board

fractional spur compensation.

The patented spur compensation circuitry designed into the

device ensures superior spur performance over the full

temperature and VCO tuning range.

The PE3293 provides fractional-N division with power-of-two

denominator values up to 32. This allows comparison

frequencies up to 32 times the channel spacing, providing a

lower phase noise floor than integer PLLs. The 32/33 RF

prescaler (PLL1) operates up to 1800 MHz and the 16/17 IF

prescaler (PLL2) operates up to 550 MHz.

The PE3293 Phase Locked-Loop is manufactured on

Peregrine’s UltraCMOS™ process, a patented variation of

silicon-on-insulator (SOI) technology on a sapphire substrate,

offering the performance of GaAs with the economy and

integration of conventional CMOS.

Figure 1. Block Diagram

1800 MHz / 550 MHz Dual Fractional-N

Ultra-Low Spurious PLL for

Frequency Synthesis

Features

•

Industry leading fractional spur

compensation: No adjusting required,

stable over temperature

•

Ultra-Low Power consumption: 4.0 mA

typical, both loops operating

•

Modulo-32 fractional-N main counters

•

Supply voltage range 2.7 to 3.3 VDC

Applications

•

Triple mode, dual-band PCS / Cellular

handset

•

PCS/CDMA/Cellular handsets

•

PCS/CDMA/Cellular base stations

32/33

Prescaler

19-bit Fractional-N

Main Divider

Fractional Spur

Compensation

Ref.

Amp.

9-bit Reference

Divider

Phase

Detector

Charge

Pump

CP1

Clock

Data

21-bit Serial Control

Interface

Multiplexer

9-bit Reference

Divider

Phase

Detector

Charge

Pump

CP2

16/17

Prescaler

18-bit Fractional-N

Main Divider

Fractional Spur

Compensation

Document No. 70-0015-03

│

www.psemi.com

Page 1 of 13

3293-11 Related Products

	3293-11	3293-12
Description	Phase Locked Loop, CMOS, PDSO20, 0.65 MM PITCH, MO-153AC, TSSOP-20	Phase Locked Loop, CMOS, PDSO20, 0.65 MM PITCH, MO-153AC, TSSOP-20
Maker	pSemi (peregrine semiconductor)	pSemi (peregrine semiconductor)
Parts packaging code	TSSOP	TSSOP
package instruction	0.65 MM PITCH, MO-153AC, TSSOP-20	0.65 MM PITCH, MO-153AC, TSSOP-20
Contacts	20	20
Reach Compliance Code	compliant	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP	PHASE LOCKED LOOP
JESD-30 code	R-PDSO-G20	R-PDSO-G20
length	6.5 mm	6.5 mm
Number of functions	1	1
Number of terminals	20	20
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	3.3 V	3.3 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
width	4.4 mm	4.4 mm
Base Number Matches	1	1

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