71024S20TY datasheet, PDF - EEWORLD Datasheet

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71024S20TY: DescriptionStandard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32; Categorystorage storage; File Size680KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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71024S20TY Overview

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

71024S20TY Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOJ
package instruction	0.300 INCH, PLASTIC, SOJ-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	R-PDSO-J32
JESD-609 code	e0
length	20.96 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Encapsulate equivalent code	SOJ32,.34
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.759 mm
Maximum standby current	0.01 A
Minimum standby current	4.5 V
Maximum slew rate	0.14 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.62 mm
Base Number Matches	1

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CMOS Static RAM

1 Meg (128K x 8-Bit)

Features

128K x 8 advanced high-speed CMOS static RAM

Commercial (0°C to +70°C), Industrial (–40°C to +85°C)

Equal access and cycle times

— Commercial and Industrial: 12/15/20ns

Two Chip Selects plus one Output Enable pin

Bidirectional inputs and outputs directly

TTL-compatible

Low power consumption via chip deselect

Available in 300 and 400 mil Plastic SOJ.

IDT71024S/MS

◆

Description

The IDT71024 is a 1,048,576-bit high-speed static RAM organized as

128K x 8. It is fabricated using IDT’s high-performance, high-reliability

CMOS technology. This state-of-the-art technology, combined with inno-

vative circuit design techniques, provides a cost-effective solution for high-

speed memory needs.

The IDT71024 has an output enable pin which operates as fast

as 6ns, with address access times as fast as 12ns available. All

bidirectional inputs and outputs of the IDT71024 are TTL-compat-

ible, and operation is from a single 5V supply. Fully static asynchro-

nous circuitry is used; no clocks or refreshes are required for

operation.

The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-

pin 400 mil Plastic SOJ.

◆

Functional Block Diagram

•

ADDRESS

DECODER

•

1,048,576-BIT

MEMORY ARRAY

I/O

0–

I/O

I/O CONTROL

CONTROL

LOGIC

2964 drw 01

OCTOBER 2008

DSC-2964/17

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