Product Specification
PE83512
Product Description
The PE83512 is a high-performance static
UltraCMOS™
prescaler with a fixed divide ratio of 4. Its operating frequency
range is DC to 1500 MHz. The PE83512 operates on a nominal
3 V supply and draws only 14 mA. It is packaged in a small
8-lead plastic MSOP and is ideal for frequency scaling and
clock generation solutions.
The PE83512 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
DC - 1500 MHz Low Power UltraCMOS™
Divide-by-4 Prescaler
Military Operating Temperature Range
Features
•
DC to 1500 MHz operation
•
Fixed divide ratio of 4
•
Low-power operation: 14 mA typical
@ 3.0 V
•
Ultra small package: 8-lead MSOP
Figure 2. Package Type
8-lead MSOP
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω
)
2.85 V
≤
V
DD
≤
3.15 V; -55° C
≤
T
A
≤
125° C, unless otherwise specified
Parameter
Supply Voltage
Conditions
Minimum
2.85
Typical
3.0
7
14
Maximum
3.15
12
25
1500
+10
+10
+10
Units
V
mA
mA
MHz
dBm
dBm
dBm
dBm
OUTB Disabled
Supply Current
1
OUTB Enabled
Input Frequency (F
IN
)
100 MHz
≤
F
in
≤
1200 MHz
-55°C
≤
T
A
≤
85°C
100 MHz
≤
F
in
≤
1200 MHz
85°C
≥
T
A
≥
125°C
1200 MHz < F
in
≤
1500 MHz
-55°C
≤
T
A
≤
85°C
DC < Fin
≤
1500 MHz
DC
-5
0
+5
+2
Input Power (P
IN
)
Output Power
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
PE83512
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
V
DD
1
2
8
7
GND
IN
OUT
PE83512
N/C
3
4
6
5
CTL
GND
OUT
Table 2. Pin Descriptions
Pin No.
1
2
3
Pin
Name
V
DD
IN
N/C
Device Functional Considerations
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left
open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Inverted divided frequency output. This pin
should be coupled with a capacitor
(eg 1000 pF).
Control pin. When grounded OUTB is
enabled.
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 1000 pF).
Ground Pin.
4
GND
The
PE83512
divides an input signal, up to a
frequency of 1500 MHz, by a factor of four thereby
producing an output frequency at one fourth the
input frequency. To work properly at higher
frequency, the input and output signals (pins 2 , 7
& optional 5) must be AC coupled via an external
capacitor. The input may be DC coupled for low
frequency operation with care taken to remain
within the specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 8 for a layout example.
OUTB Control
Pin 6 controls whether OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will use roughly 5 mA
more current.
5
OUTB
6
CTL
7
8
OUT
GND
Table 3. Absolute Maximum Ratings
Symbol
V
DD
P
in
V
IN
T
ST
T
OP
V
ESD
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883)
Min
Max
4.0
15
V
DD
+0.3
150
125
2000
Units
V
dBm
V
°C
°C
V
-0.3
-65
-55
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0117-03
│
UltraCMOS™ RFIC Solutions
PE83512
Product Specification
Typical Performance Data: V
DD
= 3.0 V
Figure 4. Input Sensitivity
Figure 5. Device Current (OUTB Enabled)
Figure 6. Output Power (OUT or OUTB)
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Page 3 of 7
PE83512
Product Specification
Evaluation Kit
Evaluation Kit Operation
The
PE83512
EK board was designed to ease
customer evaluation of Peregrine’s high performance
Military Grade divide-by-4 Prescaler. On this board,
the device input (pin 2) is connected via J1 and a 50
Ω
transmission line. A series capacitor (C3) provides the
necessary DC block for the device input. It is important
to note that the value of this capacitance will impact the
performance of the device. A value of 1000 pF was
found to be optimal for this board layout; other
applications may require a different value.
The device output (pin 7) is connected to connector J3
through a 50
Ω
transmission line. A series capacitor
(C1) provides the necessary DC block for the device
output. Note that this capacitor must be chosen to
have low impedance at the desired output frequency
the device. The value of 1000pF was chosen to
provide a wide operating range for the evaluation
board.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4. Note
that the predominate mode for these transmission lines
is coplanar waveguide.
J2 provides DC power to the device. Starting from the
lower left pin, the second pin to the right (J2-3) is
connected to the device VDD pin (1). Two decoupling
capacitors (10pF, 1000pF) are included on this trace. It
is the responsibility of the customer to determine proper
supply decoupling for their design application.
Applications Support
If you have a problem with your evaluation kit or if you
have applications questions call (858) 731-9400 and
ask for applications support. You may also contact us
by fax or e-mail:
Fax:
(858) 731-9499
E-Mail:
help@psemi.com
Figure 7. Evaluation Board Layouts
Peregrine Specification 101/0190
Figure 8. Evaluation Board Schematic
Peregrine Specification 102/0201
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0117-03
│
UltraCMOS™ RFIC Solutions
PE83512
Product Specification
Figure 9. Package Drawing
8-lead MSOP
TOP VIEW
0.65BSC
8
7
6
5
.525BSC
2.45±0.10
2X
3.00±0.10
0.51±0.13
-B-
1
2
3
4
.25 A B C
0.51±0.13
2.95±0.10
-C-
0.86±0.08
2.95±0.10
1.10 MAX
-A-
0.10 A
0.33+0.07
-0.08
0.08
A B C
3.00±0.10
FRONT VIEW
SIDE VIEW
0.10±0.05
3.00±0.10
4.90±0.15
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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