a
KEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
160 MIPS Sustained Performance
40K Words of On-Chip RAM, Configured as 32K Words
On-Chip 24-Bit Program RAM and 8K Words On-Chip
16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full Speed Operation from Low
Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
with up to 20 MSPS Sampling Rate (at 160 MHz Core
Clock Rate)
Mixed Signal DSP Controller
ADSP-21991
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0 V Voltage Reference
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GENERATOR/PLL
JTAG
TEST AND
EMULATION
ADSP-219x
DSP CORE
32K 24
PM RAM
8K 16
DM RAM
4K 24
PM ROM
ADDRESS
EXTERNAL
MEMORY
INTERFACE
(EMI)
I/O
BUS
DATA
CONTROL
PM ADDRESS/DATA
DM ADDRESS/DATA
I/O REGISTERS
SPI
SPORT
MEMORY DMA
CONTROLLER
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
TIMER 0
AUXILIARY
PWM
UNIT
TIMER 1
TIMER 2
FLAG
I/O
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
ADC
CONTROL
PIPELINE
FLASH ADC
POR
VREF
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
©
2003 Analog Devices, Inc. All rights reserved.
ADSP-21991
KEY FEATURES (continued)
Integrated Power-On-Reset (POR) Generator
Flexible Power Management with Selectable Power-
Down and Idle Modes
2.5 V Internal Operation with 3.3 V I/O
Operating Temperature Range of –40ºC to +85ºC
196-Ball Mini-BGA Package
176-Lead LQFP Package
TARGET APPLICATIONS
Industrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5
External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5
External Memory Space . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . 6
Serial Peripheral Interface (SPI) Port . . . . . . . . . . . . . 7
DSP Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . 7
Analog-to-Digital Conversion System . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PWM Generation Unit . . . . . . . . . . . . . . . . . . . . . . . 8
Auxiliary PWM Generation Unit . . . . . . . . . . . . . . . . 9
Encoder Interface Unit . . . . . . . . . . . . . . . . . . . . . . . 9
Flag I/O (FIO) Peripheral Unit . . . . . . . . . . . . . . . . 10
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . 10
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral Interrupt Controller . . . . . . . . . . . . . . . . 11
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 11
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-Down Core Mode . . . . . . . . . . . . . . . . . . . 11
Power-Down Core/Peripherals Mode . . . . . . . . . . 12
Power-Down All Mode . . . . . . . . . . . . . . . . . . . . 12
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Power-On Reset (POR) . . . . . . . . . . . . . . 12
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Set Description . . . . . . . . . . . . . . . . . . . 13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 13
Designing an Emulator-Compatible DSP Board . . . 14
Additional Information . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 14
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 22
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 22
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . .
Clock In and Clock Out Cycle Timing . . . . . . . . .
Programmable Flags Cycle Timing . . . . . . . . . . .
Timer PWM_OUT Cycle Timing . . . . . . . . . . . .
External Port Write Cycle Timing . . . . . . . . . . . .
External Port Read Cycle Timing . . . . . . . . . . . .
External Port Bus Request/Grant Cycle Timing . .
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface Port—Master Timing .
Serial Peripheral Interface Port—Slave Timing . .
JTAG Test And Emulation Port Timing . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . .
Example System Hold Time Calculation . . . . . . .
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION
22
23
24
25
26
27
28
29
32
33
34
35
35
35
35
35
36
41
42
The ADSP-21991 is a mixed signal DSP controller based on the
ADSP-219x DSP Core, suitable for a variety of high performance
industrial motor control and signal processing applications that
require the combination of a high performance DSP and the
mixed signal integration of embedded control peripherals such
as analog-to-digital conversion.
The ADSP-21991 integrates the fixed point ADSP-219x family
base architecture with a serial port, an SPI compatible port, a
DMA controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities, on-
chip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21991 architecture is code compatible with previous
ADSP-217x based ADMCxxx products. Although the architec-
tures are compatible, the ADSP-21991, with ADSP-219x
architecture, has a number of enhancements over earlier archi-
tectures. The enhancements to computational units, data address
generators, and program sequencer make the ADSP-21991 more
flexible and easier to program than the previous ADSP-21xx
embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for easier
implementation of circular buffering.
The ADSP-21991 integrates 40K words of on-chip memory con-
figured as 32K words (24-bit) of program RAM, and 8K words
(16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21991 operates with a 6.25 ns instruction cycle time for
a 160 MHz CCLK and with a 6.67 ns instruction cycle time for
a 150 MHz CCLK. All instructions, except two multiword
instructions, execute in a single DSP cycle.
–2–
REV. 0
ADSP-21991
The flexible architecture and comprehensive instruction set of
the ADSP-21991 support multiple operations in parallel. For
example, in one processor cycle, the ADSP-21991 can:
•
Generate an address for the next instruction fetch
•
Fetch the next instruction
•
Perform one or two data moves
•
Update one or two data address pointers
•
Perform a computational operation
These operations take place while the processor continues to:
•
Receive and transmit data through the serial port
•
Receive or transmit data over the SPI port
•
Access external memory through the external memory
interface
•
Decrement the timers
•
Operate the embedded control peripherals (ADC, PWM,
EIU, etc.)
DSP Core Architecture
The clock generator module of the ADSP-21991 includes clock
control logic that allows the user to select and change the main
clock frequency. The module generates two output clocks: the
DSP core clock, CCLK; and the peripheral clock, HCLK.
CCLK can sustain clock values of up to 160 MHz, while HCLK
can be equal to CCLK or CCLK/2 for values up to a maximum
80 MHz peripheral clock at the 160 MHz CCLK rate.
The ADSP-21991 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single word instruction can be executed in a
single processor cycle. The ADSP-21991 assembly language uses
an algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
The block diagram
Figure 1
shows the architecture of the
embedded ADSP-219x core. It contains three independent com-
putational units: the ALU, the multiplier/accumulator (MAC),
and the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating point representations.
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21991 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four 16-bit
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
–3–
•
6.25 ns instruction cycle time (internal), for up to
160 MIPS sustained performance (6.67 ns instruction
cycle time for 150 MIPS sustained performance)
•
ADSP-218x family code compatible with the same easy
to use algebraic syntax
•
Single cycle instruction execution
•
Up to 1M words of addressable memory space with
twenty four bits of addressing width
•
Dual purpose program memory for both instruction and
data storage
•
Fully transparent instruction cache allows dual operand
fetches in every instruction cycle
•
Unified memory space permits flexible address genera-
tion, using two independent DAG units
•
Independent ALU, multiplier/accumulator, and barrel
shifter computational units with dual 40-bit accumulators
•
Single cycle context switch between two sets of computa-
tional and DAG registers
•
Parallel execution of computation and memory
instructions
•
Pipelined architecture supports efficient code execution
at speeds up to 160 MIPS
•
Register file computations with all nonconditional, non-
parallel computational instructions
•
Powerful program sequencer provides zero overhead
looping and conditional instruction execution
•
Architectural enhancements for compiled C code
efficiency
•
Architecture enhancements beyond ADSP-218x family
are supported with instruction set extensions for added
registers, ports, and peripherals.
REV. 0
ADSP-21991
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
DATA
ADDRESS 24 BIT
DATA
ADDRESS 24 BIT
ADDRESS 16 BIT
DATA
DATA
ADDRESS 16 BIT
BLOCK0
BLOCK1
BLOCK3
ADSP-219x DSP CORE
CACHE
64 24-BIT
DAG1
DAG2
4 16 4 4 16
PROGRAM
SEQUENCER
BLOCK2
JTAG
TEST AND
EMULATION
6
4
EXTERNAL PORT
I/O ADDRESS 18
ADDR BUS
MUX
PM ADDRESS BUS
24
DM ADDRESS BUS 24
DMA CONNECT
PX
PM DATA BUS
DATA
REGISTER
FILE
24
DM DATA BUS 16
I/O DATA
INPUT
REGISTERS
RESULT
REGISTERS
16 16-BIT
16
I/O REGISTERS
(MEMORY-MAPPED)
BARREL
SHIFTER
ALU
CONTROL
STATUS
BUFFERS
DMA CONTROLLER
SYSTEM INTERRUPT
CONTROLLER
PROGRAMMABLE
FLAGS (16)
TIMERS
(3)
3
I/O PROCESSOR
EMBEDDED
CONTROL
PERIPHERALS
AND
COMMUNICATIONS
PORTS
DMA ADDRESS 24
DMA DATA 24
DATA BUS
MUX
16
20
MULT
Figure 1. Block Diagram
Efficient data transfer in the core is achieved with the use of
internal buses:
•
Program Memory Address (PMA) Bus
•
Program Memory Data (PMD) Bus
•
Data Memory Address (DMA) Bus
•
Data Memory Data (DMD) Bus
•
Direct Memory Access Address Bus
•
Direct Memory Access Data Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21991 to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP
dual memory buses also let the embedded ADSP-219x core fetch
an operand from data memory and the next instruction from
program memory in a single cycle.
Memory Architecture
The ADSP-21991 provides 40K words of on-chip SRAM
memory. This memory is divided into three blocks: two
16K
×
24-bit blocks (blocks 0 and 1) and one 8K
×
16-bit block
(block 2). In addition, the ADSP-21991 provides a 4K
×
24-bit
block of program memory boot ROM (that is reserved by ADI
for boot load routines). The memory map of the ADSP-21991
is illustrated in Figure 2.
As shown in Figure 2, the three internal memory RAM blocks
reside in memory page 0. The entire DSP memory map consists
of 256 pages (pages 0 to 255), and each page is 64K words long.
External memory space consists of four memory banks
(banks3–0) and supports a wide variety of memory devices. Each
bank is selectable using unique memory select lines (MS3–0) and
has configurable page boundaries, wait states, and wait state
modes. The 4K words of on-chip boot ROM populates the top
of page 255, while the remaining 254 pages are addressable off-
chip. I/O memory pages differ from external memory in that they
are 1K word long, and the external I/O pages have their own select
pin (IOMS). Pages 31–0 of I/O memory space reside on-chip and
–4–
REV. 0
ADSP-21991
contain the configuration registers for the peripherals. Both the
ADSP-219x core and DMA capable peripherals can access the
entire memory map of the DSP.
calls, and loops on the 24-bit program counter (PC). In
direct addressing instructions (two word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
•
For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer IJPG register to the
appropriate memory page.
The ADSP-21991 has 4K word of on-chip ROM that holds boot
routines. The DSP starts executing instructions from the on-chip
boot ROM, which starts the boot process.
See Booting Modes
on Page 13.
The on-chip boot ROM is located on Page 255 in
the DSP memory space map, starting at address 0xFF0000.
External (Off-Chip) Memory
EXTERNAL MEMORY
(4M–64K)
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
0x00 0000
0x00 3FFF
0x00 4000
0x00 7FFF
0x00 8000
0x00 9FFF
0x00 A000
0x00 FFFF
0x01 0000
BLOCK 0: 16K
BLOCK 1: 16K
BLOCK 2: 8K
24-BIT PM RAM
24-BIT PM RAM
16-BIT DM RAM
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
RESERVED (24K)
EXTERNAL MEMORY
(4M–64K)
0x40 0000
PAGES 1 TO 63 BANK 0
(OFF-CHIP)
MS0
PAGES 64 TO 127 BANK 1
(OFF-CHIP)
MS1
PAGES 128 TO 191 BANK 2
(OFF-CHIP)
MS2
PAGES 192 TO 254 BANK 3
(OFF-CHIP)
MS3
EXTERNAL MEMORY (4M)
0x80 0000
EXTERNAL MEMORY (4M)
0xC0 0000
BLOCK 3: 4K 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
PAGE 255
(INCLUDES ON-CHIP BOOT ROM)
Figure 2. Core Memory Map at Reset
Each of the off-chip memory spaces of the ADSP-21991 has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, wait state completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths.
See Clock Signals on
Page 12.
The off-chip memory spaces are:
•
External memory space (MS3–0 pins)
•
I/O memory space (IOMS pin)
•
Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for 8-bit or 16-bit data
widths.
External Memory Space
NOTE: The physical external memory addresses are limited by
20 address lines, and are determined by the external data width
and packing of the external memory space. The Strobe signals
(MS3-0) can be programmed to allow the user to change starting
page addresses at run time.
Internal (On-Chip) Memory
The unified program and data memory space of the ADSP-21991
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA, and DMA buses. The DSP uses slightly
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
•
The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A “C”
program macro is provided for setting this register.
•
The program sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0 con-
taining pages 1 to 63, Bank1 containing pages 64 to 127, Bank2
containing pages 128 to 191, and Bank3 containing pages 192 to
254. The
MS3-0
memory bank pins select Banks 3-0, respec-
tively. Both the ADSP-219x core and DMA capable peripherals
can access the DSP external memory space.
All accesses to external memory are managed by the External
Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21991 supports an additional external memory
called I/O memory space. The IO space consists of 256 pages,
each containing 1024 addresses. This space is designed to
support simple connections to peripherals (such as data convert-
ers and external registers) or to bus interface ASIC data registers.
The first 32K addresses (IO pages 0 to 31) are reserved for
on-chip peripherals. The upper 224K addresses (IO pages 32 to
REV. 0
–5–
Microchip MCU
京公网安备 11010802033920号
EEWORLD
