2. Enhanced Configuration
Devices (EPC4, EPC8 &
EPC16) Data Sheet
CF52002-2.1
Features
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Enhanced configuration devices include EPC4, EPC8, and EPC16
devices
Single-chip configuration solution for Stratix
®
series, Cyclone™
series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and
APEX 20KE), Mercury™, ACEX
®
1K, and FLEX
®
10K (FLEX 10KE
and FLEX 10KA) devices
Contains 4-, 8-, and 16-Mbit flash memories for configuration data
storage
On-chip decompression feature almost doubles the effective
●
configuration density
Standard flash die and a controller die combined into single stacked
chip package
External flash interface supports parallel programming of flash and
external processor access to unused portions of memory
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Flash memory block/sector protection capability via external
flash interface
●
Supported in EPC16 and EPC4 devices
Page mode support for remote and local reconfiguration with up to
eight configurations for the entire system
Compatible with Stratix series Remote System Configuration
●
feature
Supports byte-wide configuration mode fast passive parallel (FPP);
8-bit data output per
DCLK
cycle
Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of
Altera FPGAs
Pin-selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and
frequency synthesis
●
Multiple configuration clock sources supported (internal
oscillator and external clock input pin)
●
External clock source with frequencies up to 133 MHz
Internal oscillator defaults to 10 MHz; Programmable for higher
●
frequencies of 33, 50, and 66 MHz
Clock synthesis supported via user programmable divide
●
counter
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin
Ultra FineLine BGA
®
packages
Vertical migration between all devices supported in the 100-pin
●
PQFP package
Supply voltage of 3.3 V (core and I/O)
Altera Corporation
August 2005
2–1
Functional Description
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Hardware compliant with IEEE Std. 1532 in-system
programmability (ISP) specification
Supports ISP via Jam Standard Test and Programming Language
(STAPL)
Supports Joint Test Action Group (JTAG) boundary scan
nINIT_CONF
pin allows private JTAG instruction to initiate FPGA
configuration
Internal pull-up resistor on
nINIT_CONF
always enabled
User programmable weak internal pull-up resistors on
nCS
and
OE
pins
Internal weak pull-up resistors on external flash interface address
and control lines, bus hold on data lines
Standby mode with reduced power consumption
f
For more information on FPGA configuration schemes and advanced
features, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
The Altera enhanced configuration device is a single-device, high-speed,
advanced configuration solution for very high-density FPGAs. The core
of an enhanced configuration device is divided into two major blocks, a
configuration controller and a flash memory. The flash memory is used to
store configuration data for systems made up of one or more Altera
FPGAs. Unused portions of the flash memory can be used to store
processor code or data that can be accessed via the external flash interface
after FPGA configuration is complete.
1
The external flash interface is currently supported in the EPC16
and EPC4 devices. For information on using this feature in the
EPC8 device, contact Altera Applications.
Functional
Description
The enhanced configuration device has a 3.3-V core and I/O interface.
The controller chip is a synchronous system that implements the various
interfaces and features.
Figure 2–1
shows a block diagram of the
enhanced configuration device. The controller chip features three
separate interfaces:
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A configuration interface between the controller and the Altera
FPGA(s)
A JTAG interface on the controller that enables in-system
programmability (ISP) of the flash memory
An external flash interface that the controller shares with an external
processor, or FPGA implementing a Nios
®
embedded processor
(interface available after ISP and configuration)
2–2
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Figure 2–1. Enhanced Configuration Device Block Diagram
JTAG/ISP Interface
Enhanced Configuration Device
Shared Flash
Interface
Flash
Controller
FPGA
Shared Flash Interface
The enhanced configuration device features multiple configuration
schemes. In addition to supporting the traditional passive serial (PS)
configuration scheme for a single device or a serial device chain, the
enhanced configuration device features concurrent configuration and
parallel configuration. With the concurrent configuration scheme, up to
eight PS device chains can be configured simultaneously. In the FPP
configuration scheme, 8-bits of data are clocked into the FPGA each cycle.
These schemes offer significantly reduced configuration times over
traditional schemes.
Furthermore, the enhanced configuration device features a dynamic
configuration or page mode feature. This feature allows you to
dynamically reconfigure all the FPGAs in your system with new images
stored in the configuration memory. Up to eight different system
configurations or pages can be stored in memory and selected using the
PGM[2..0]
pins. Your system can be dynamically reconfigured by
selecting one of the eight pages and initiating a reconfiguration cycle.
This page mode feature combined with the external flash interface allows
remote and local updates of system configuration data. The enhanced
configuration devices are compatible with the Stratix Remote System
Configuration feature.
Altera Corporation
August 2005
2–3
Configuration Handbook, Volume 2
Functional Description
1
For more information on Stratix Remote System Configuration,
refer to the
Using Remote System Configuration with Stratix &
Stratix GX Devices chapter of the Stratix Device Handbook.
Other user programmable features include:
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Real-time decompression of configuration data
Programmable configuration clock (DCLK)
Flash ISP
Programmable power-on-reset delay (PORSEL)
FPGA Configuration
FPGA configuration is managed by the configuration controller chip.
This process includes reading configuration data from the flash memory,
decompressing it if necessary, transmitting configuration data via the
appropriate
DATA[]
pins, and handling errors conditions.
After POR, the controller determines the user-defined configuration
options by reading its option bits from the flash memory. These options
include the configuration scheme, configuration clock speed,
decompression, and configuration page settings. The option bits are
stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the
internal flash interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, it checks if the FPGA is ready
to accept configuration data by monitoring the
nSTATUS
and
CONF_DONE
lines. When the FPGA is ready (nSTATUS is high and
CONF_DONE
is low), the controller begins data transfer using the
DCLK
and
DATA[]
output pins. The controller selects the configuration page to
be transmitted to the FPGA(s) by sampling its
PGM[2..0]
pins after POR
or reset.
The function of the configuration unit is to transmit decompressed data
to the FPGA, depending on the configuration scheme. The enhanced
configuration device supports four concurrent configuration modes, with
n = 1, 2, 4, or 8 (where n is the number of bits that are sent per
DCLK
cycle
on the
DATA[n]
lines). The value n=1 corresponds to the traditional PS
configuration scheme. The values n=2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively.
Additionally, the FPGA can be configured in FPP mode, where eight bits
of
DATA
are clocked into the FPGA per
DCLK
cycle. Depending on the
configuration bus width (n), the circuit shifts uncompressed
configuration data to the valid
DATA[n]
pins. Unused
DATA[]
pins drive
low.
2–4
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
In addition to transmitting configuration data to the FPGAs, the
configuration circuit is also responsible for pausing configuration
whenever there is insufficient data available for transmission. This occurs
when the flash read bandwidth is lower than the configuration write
bandwidth. Configuration is paused by stopping the
DCLK
to the FPGA,
when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing
DCLK.”
The enhanced configuration device flash memories feature a 90-ns access
time (approximately 10 MHz). Hence, the flash read bandwidth is limited
to about 160 megabits per second (Mbps) (16-bit flash data bus,
DQ[],
at
10 MHz). However, the configuration speeds supported by Altera FPGAs
are much higher and translate to high configuration write bandwidths.
For instance, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit
DATA[]
bus at 100 MHz). This is much higher than the
160 Mbps the flash memory can support, and is the limiting factor for
configuration time. Compression increases the effective flash read
bandwidth since the same amount of configuration data takes up less
space in the flash memory after compression. Since Stratix configuration
data compression ratios are approximately two, the effective read
bandwidth doubles to about 320 Mbps.
Finally, the configuration controller also manages errors during
configuration. A
CONF_DONE
error occurs when the FPGA does not de-
assert its
CONF_DONE
signal within 64 DCLK cycles after the last bit of
configuration data is transmitted. When a
CONF_DONE
error is detected,
the controller pulses the
OE
line low, which pulls
nSTATUS
low and
triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects
corruption in the configuration data. This corruption could be a result of
noise coupling on the board such as poor signal integrity on the
configuration signals. When this error is signaled by the FPGA (by
driving the
nSTATUS
line low), the controller stops configuration. If the
Auto-Restart Configuration After Error
option is enabled in the FPGA,
it releases its
nSTATUS
signal after a reset time-out period and the
controller attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives
DCLK
low and the
DATA[]
pins high. Additionally, the controller tri-
states its internal interface to the flash memory, enables the weak internal
pull-ups on the flash address and control lines, and enables bus-keep
circuits on flash data lines.
The following sections briefly describe the different configuration
schemes supported by the enhanced configuration device: FPP, PS, and
concurrent configuration.
Altera Corporation
August 2005
2–5
Configuration Handbook, Volume 2
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