7130SA100PGB datasheet, PDF - EEWORLD Datasheet

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7130SA100PGB: DescriptionDual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, GREEN, PLASTIC, DIP-48; Categorystorage; File Size148KB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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7130SA100PGB Overview

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, GREEN, PLASTIC, DIP-48

7130SA100PGB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	DIP,
Contacts	48
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	100 ns
JESD-30 code	R-PDIP-T48
JESD-609 code	e3
length	61.849 mm
memory density	8192 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Number of functions	1
Number of terminals	48
word count	1024 words
character code	1000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Filter level	MIL-PRF-38535
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	15.24 mm
Base Number Matches	1

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HIGH SPEED

1K X 8 DUAL-PORT

STATIC SRAM

Features

◆

IDT7130SA/LA

IDT7140SA/LA

◆

High-speed access

– Commercial: 20/25/35/55/100ns (max.)

– Industrial: 25/55/100ns (max.)

– Military: 25/35/55/100ns (max.)

Low-power operation

– IDT7130/IDT7140SA

—

Active: 550mW (typ.)

—

Standby: 5mW (typ.)

– IDT7130/IDT7140LA

—

Active: 550mW (typ.)

—

Standby: 1mW (typ.)

MASTER IDT7130 easily expands data bus width to 16-or-

more-bits using SLAVE IDT7140

◆

On-chip port arbitration logic (IDT7130 Only)

BUSY

output flag on IDT7130;

BUSY

input on IDT7140

INT

flag for port-to-port communication

Fully asynchronous operation from either port

Battery backup operation–2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin

PLCC, and 64-pin STQFP and TQFP

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

(1,2)

I/O

-I/O

I/O

Control

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

R/W

ARBITRATION

and

INTERRUPT

LOGIC

R/W

INT

(2)

INT

2689 drw 01

(2)

NOTES:

1. IDT7130 (MASTER):

BUSY

is open drain output and requires pullup resistor.

IDT7140 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup resistor.

OCTOBER 2008

DSC-2689/14

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