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74AC04

Description
AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
Categorysemiconductor    logic   
File Size297KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

74AC04 Overview

AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14

74AC04 Parametric

Parameter NameAttribute value
Number of functions6
Number of terminals14
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage6 V
Minimum supply/operating voltage2 V
Rated supply voltage3.3 V
Processing package description0.150 INCH, Lead FREE, MS-012AB, SOIC-14
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
seriescomminicate
Logic IC typeNo
Number of inputs1
propagation delay TPD10 ns
74AC04, 74ACT04 Hex Inverter
74AC04, 74ACT04
Hex Inverter
Features
I
CC
reduced by 50% on 74AC only
Outputs source/sink 24mA
ACT04 has TTL-compatible inputs
September
2007
tm
General Description
The AC/ACT04 contains six inverters.
Ordering Information
Order
Number
74AC04SC
74AC04SJ
74AC04MTC
74AC04PC
74ACT04SC
74ACT04MTC
74ACT04PC
Package
Number
M14A
M14D
MTC14
N14A
M14A
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in
Tape and Reel.)
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
O
n
Description
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
74AC04, 74ACT04 Rev. 1.0
www.fairchildsemi.com

74AC04 Related Products

74AC04 74AC04_07 74ACT04 74AC04SC 74ACT04SC 74AC04PC 74AC04MTC
Description AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14 AC SERIES, HEX 1-INPUT INVERT GATE, PDIP14 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
Number of functions 6 6 6 6 6 6 6
Number of terminals 14 14 14 14 14 14 14
Maximum operating temperature 85 Cel 85 Cel 85 Cel 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 Cel -40 Cel -40 Cel -40 °C -40 °C -40 °C -40 °C
surface mount Yes Yes Yes YES YES NO YES
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING THROUGH-HOLE GULL WING
Terminal location pair pair pair DUAL DUAL DUAL DUAL
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
series comminicate comminicate comminicate AC ACT AC AC
Brand Name - - - Fairchild Semiconduc Fairchild Semiconduc Fairchild Semiconduc Fairchild Semiconduc
Is it lead-free? - - - Lead free Lead free Lead free Lead free
Is it Rohs certified? - - - conform to conform to conform to conform to
Parts packaging code - - - SOIC SOIC DIP TSSOP
package instruction - - - SOP, SOP14,.25 SOP, SOP14,.25 DIP, DIP14,.3 TSSOP, TSSOP14,.25
Contacts - - - 14 14 14 14
Manufacturer packaging code - - - 14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY 14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY 14LD, MDIP,JEDEC MS-001, .300\" WIDE 14 LD,TSSOP,JEDEC MO-153, 4.4MM WIDE
Reach Compliance Code - - - compli compli unknow compli
ECCN code - - - EAR99 EAR99 EAR99 EAR99
JESD-30 code - - - R-PDSO-G14 R-PDSO-G14 R-PDIP-T14 R-PDSO-G14
JESD-609 code - - - e3 e3 e3 e4
length - - - 8.6 mm 8.6 mm 19.18 mm 5 mm
Load capacitance (CL) - - - 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type - - - INVERTER INVERTER INVERTER INVERTER
MaximumI(ol) - - - 0.012 A 0.024 A 0.012 A 0.012 A
Number of entries - - - 1 1 1 1
Package body material - - - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - - - SOP SOP DIP TSSOP
Encapsulate equivalent code - - - SOP14,.25 SOP14,.25 DIP14,.3 TSSOP14,.25
Package shape - - - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - - - SMALL OUTLINE SMALL OUTLINE IN-LINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) - - - NOT SPECIFIED NOT SPECIFIED NOT APPLICABLE 260
power supply - - - 3.3/5 V 5 V 3.3/5 V 3.3/5 V
Prop。Delay @ Nom-Su - - - 10 ns 9 ns 10 ns 10 ns
propagation delay (tpd) - - - 10 ns 9 ns 10 ns 10 ns
Certification status - - - Not Qualified Not Qualified Not Qualified Not Qualified
Schmitt trigger - - - NO NO NO NO
Maximum seat height - - - 1.75 mm 1.75 mm 5.08 mm 1.2 mm
Maximum supply voltage (Vsup) - - - 6 V 5.5 V 6 V 6 V
Minimum supply voltage (Vsup) - - - 2 V 4.5 V 2 V 2 V
Nominal supply voltage (Vsup) - - - 3.3 V 5 V 3.3 V 3.3 V
technology - - - CMOS CMOS CMOS CMOS
Terminal surface - - - Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal pitch - - - 1.27 mm 1.27 mm 2.54 mm 0.65 mm
Maximum time at peak reflow temperature - - - NOT SPECIFIED NOT SPECIFIED NOT APPLICABLE NOT SPECIFIED
width - - - 3.9 mm 3.9 mm 7.62 mm 4.4 mm
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