LF
PSMN6R5-30MLD
11 August 2015
PA
K
33
N-channel 30 V, 6.5 mΩ logic level MOSFET in LFPAK33
using NextPowerS3 Technology
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK33 package.
NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETS with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
•
•
•
•
•
•
•
•
Ultra low Q
G
, Q
GD
and Q
OSS
for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Mini Power SO8 package; no glue,
no wire bonds, qualified to 175 °C
Exposed leads for optimal visual solder inspection
3. Applications
•
•
•
•
•
•
On-board DC-to-DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
25 °C ≤ T
j
≤ 175 °C
T
mb
= 25 °C; V
GS
= 10 V;
Fig. 2
T
mb
= 25 °C;
Fig. 1
Min
-
-
-
Typ
-
-
-
Max
30
65
51
Unit
V
A
W
Scan or click this QR code to view the latest information for this product
NXP Semiconductors
PSMN6R5-30MLD
N-channel 30 V, 6.5 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
T
j
R
DSon
Parameter
junction temperature
Conditions
Min
-55
Typ
-
Max
175
Unit
°C
Static characteristics
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 15 A; T
j
= 25 °C;
Fig. 10
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C;
Fig. 10
Dynamic characteristics
Q
GD
Q
G(tot)
gate-drain charge
total gate charge
V
GS
= 4.5 V; I
D
= 15 A; V
DS
= 15 V;
Fig. 12; Fig. 13
V
GS
= 4.5 V; I
D
= 15 A; V
DS
= 15 V;
Fig. 12; Fig. 13
Source-drain diode
S
softness factor
I
S
= 15 A; V
GS
= 0 V; dI
S
/dt = -100 A/µs;
V
DS
= 15 V;
Fig. 16
-
1.3
-
-
6.4
-
nC
-
1.7
-
nC
-
5.5
6.5
mΩ
-
7
8.6
mΩ
5. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1
2
3
4
G
mbb076
Simplified outline
Graphic symbol
D
S
LFPAK33 (SOT1210)
6. Ordering information
Table 3.
Ordering information
Package
Name
PSMN6R5-30MLD
LFPAK33
Description
Plastic single ended surface mounted package
(LFPAK33); 8 leads
Version
SOT1210
Type number
7. Marking
Table 4.
Marking codes
Marking code
6D530L
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Type number
PSMN6R5-30MLD
PSMN6R5-30MLD
Product data sheet
11 August 2015
2 / 13
NXP Semiconductors
PSMN6R5-30MLD
N-channel 30 V, 6.5 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 2
I
DM
T
stg
T
j
T
sld(M)
I
S
I
SM
E
DS(AL)S
peak drain current
storage temperature
junction temperature
peak soldering temperature
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
Conditions
25 °C ≤ T
j
≤ 175 °C
25 °C ≤ T
j
≤ 175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
Max
30
30
20
51
65
46
262
175
175
260
Unit
V
V
V
W
A
A
A
°C
°C
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 15 A;
V
sup
≤ 30 V; R
GS
= 50 Ω; unclamped;
t
p
= 146 µs
[1]
Protected by 100% test
-
-
42
262
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[1]
-
42.7
mJ
PSMN6R5-30MLD
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
11 August 2015
3 / 13
NXP Semiconductors
PSMN6R5-30MLD
N-channel 30 V, 6.5 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
120
P
der
(%)
80
03aa16
I
D
(A)
80
aaa-008449
60
40
40
20
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
Continuous drain current as a function of
mounting base temperature
I
D
(A)
10
3
aaa-008450
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10 us
100 us
10
DC
1 ms
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 4
Min
-
Typ
2.72
Max
2.94
Unit
K/W
PSMN6R5-30MLD
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
11 August 2015
4 / 13
NXP Semiconductors
PSMN6R5-30MLD
N-channel 30 V, 6.5 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
R
th(j-a)
Parameter
thermal resistance
from junction to
ambient
Conditions
Fig. 5
Fig. 6
Min
-
-
Typ
57
178
Max
-
-
Unit
K/W
K/W
Z
th(j-mb)
(K/W)
10
aaa-008451
δ = 0.5
1
0.2
0.1
0.05
10
-1
0.02
single shot
P
δ=
t
p
T
t
p
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-008476
aaa-008477
Fig. 5.
PCB layout for thermal resistance junction to
ambient 1" square pad; FR4 Board; 2oz copper
Fig. 6.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C
Min
30
27
1.2
Typ
-
-
1.68
Max
-
-
2.2
Unit
V
V
V
Static characteristics
V
GS(th)
PSMN6R5-30MLD
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet
11 August 2015
5 / 13
京公网安备 11010802033920号
EEWORLD
