Dual MOSFET Driver
with Bootstrapping
ADP3415
FEATURES
All-in-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
Programmable Transition Delay
Zero-Crossing Synchronous Drive Control
Synchronous Override Control
Undervoltage Lockout
Shutdown Quiescent Current <100 A
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
FUNCTIONAL BLOCK DIAGRAM
ADP3415
VCC
UVLO
BST
IN
SD
DLY
OVERLAP
PROTECTION
CIRCUIT
DRVH
SW
VCC
DRVL
DRVLSD
GND
GENERAL DESCRIPTION
The ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the nonisolated
synchronous buck power converter topology. Each driver size is
optimized for performance in notebook PC regulators for CPUs
in the 20 A range. The high-side driver can be bootstrapped atop
the switched node of the buck converter as needed to drive the
upper switch and is designed to accommodate the high voltage
slew rate associated with high performance, high frequency
switching. The ADP3415 features an overlapping protection
circuit (OPC); undervoltage lockout (UVLO) that holds the
switches off until the driver is assured of having sufficient voltage
for proper operation; a programmable transition delay; and a
synchronous drive disable pin. The quiescent current, when the
device is disabled, is less than 100
µA.
The ADP3415 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 10-lead
MSOP package.
5V
V
DCIN
FROM DUTY RATIO
MODULATOR
FROM SYSTEM
ENABLE CONTROL
FROM SYSTEM
STATE LOGIC
IN
SD
VCC
BST
DRVH
V
OUT
ADP3415
DRVLSD
SW
DLY
GND
DRVL
Figure 1. Typical Application Circuit
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
ADP3415–SPECIFICATIONS
Parameter
SUPPLY (VCC)
Quiescent Current
2
Shutdown Mode
Operating Mode
UNDERVOLTAGE LOCKOUT
(UVLO)
UVLO Threshold
UVLO Hysteresis
LOW-SIDE DRIVER SHUTDOWN
(DRVLSD)
Input Voltage High
3
Input Voltage Low
3
Propagation Delay
3, 4
(See Figure 3)
SHUTDOWN (SD)
Input Voltage High
3
Input Voltage Low
3
INPUT (IN)
Input Voltage High
3
Input Voltage Low
3
THERMAL SHUTDOWN (THSD)
THSD Threshold
THSD Hysteresis
HIGH-SIDE DRIVER (DRVH)
Output Resistance, DRVH–BST
Output Resistance, DRVH–SW
DRVH Transition Times
4
(See Figure 4)
DRVH Propagation Delay
4, 5
(See Figure 4)
LOW-SIDE DRIVER (DRVL)
Output Resistance, DRVL–VCC
Output Resistance, DRVL–GND
DRVL Transition Times
4
(See Figure 4)
DRVL Propagation Delay
4, 5, 6
(See Figure 4)
SW Transition Timeout
7
Zero-Crossing Threshold
Symbol
I
CCQ
1
(T
A
= 0 C to 100 C, V
CC
= 5 V, V
BST
– V
SW
= 5 V,
SD
= 5 V, C
DRVH
= C
DRVL
= 3 nF,
unless otherwise noted.)
Conditions
Min
Typ
Max
Unit
V
SD
= 0.8 V
V
SD
= 5 V, No Switching
30
1.2
65
2
µA
mA
V
CCUVLO
V
CCHUVLO
3.9
4.15
0.05
4.5
V
V
V
IH
V
IL
tpdl
DRVLSD
tpdh
DRVLSD
V
IH
V
IL
V
IH
V
IL
T
SD
T
HSD
T
J
= T
A
T
J
= T
A
2.0
20
10
2.0
0.8
2.0
0.8
165
10
1.5
0.85
20
25
22
40
1.6
1.0
25
20
30
10
1.6
3.5
2.0
30
35
40
200
70
3.0
3.0
40
30
38
25
300
0.8
50
30
V
V
ns
ns
V
V
V
V
°C
°C
Ω
Ω
ns
ns
ns
ns
ns
Ω
Ω
ns
ns
ns
ns
ns
V
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
V
BST
– V
SW
= 4.6 V
V
BST
– V
SW
= 4.6 V, V
DLY
= 0 V
R
DLY
≥
120 kΩ
10
100
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
t
SWTO
V
ZC
V
BST
– V
SW
= 4.6 V
V
BST
– V
SW
= 4.6 V
V
BST
– V
SW
= 4.6 V
V
BST
– V
SW
= 4.6 V
V
BST
– V
SW
= 4.6 V
10
130
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Including I
BSTQ
quiescent current.
3
The signal source driving the pin must have 70
µA
(typ) pull-down strength to make a high-to-low transient, and 20
µA
(typ) pull-up strength to make a low-to-high
transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard
TTL logic level source.
4
Guaranteed by characterization.
5
For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.
6
Propagation delay measured until DRVL begins its transition.
7
The turn-on of DRVL is initiated after IN goes low by either V
SW
crossing a ~1.6 V threshold or by expiration of t
SWTO
.
Specifications subject to change without notice.
–2–
REV. B
ADP3415
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V
SD,
IN,
DRVLSD
to GND . . . . . . . . . . . . . . –0.3 V to +7.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
IN
1
SD
2
10
BST
9
DRVH
TOP VIEW
DRVLSD
3
(Not to Scale)
8
SW
ADP3415
DLY
4
VCC
5
7
6
GND
DRVL
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
IN
SD
DRVLSD
DLY
VCC
DRVL
GND
SW
Function
TTL-Level Input Signal. Has primary control of the drive outputs.
Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low
and the supply current (I
CCQ
) is minimized as specified.
Drive-Low Shutdown. When
DRVLSD
is low, DRVL is kept low. When
DRVLSD
is high, DRVL is
enabled and controlled by IN and by the adaptive OPC function.
High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off
of the lower FET to turn-on of the upper FET.
Input Supply. This pin should be bypassed to GND with a ~10
µF
ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.
Ground. Should be directly connected to the ground plane, close to the source of the lower FET.
This pin should be connected to the buck switching node, close to the upper FET’s source. It is the
floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the
OPC function.
Buck Drive. Output drive for the upper (buck) FET.
Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds
this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be
an MLC type and should have substantially greater capacitance (e.g., ~ 20×) than the input capacitance
of the upper FET.
9
10
DRVH
BST
ORDERING GUIDE
Model
ADP3415LRM-REEL
ADP3415LRM-REEL7
ADP3415LRMZ-REEL*
*Z
= Pb-free part.
Temperature
Guide
0°C to 100°C
0°C to 100°C
0°C to 100°C
Package
Description
MSOP
MSOP
MSOP
Package
Option
RM-10
RM-10
RM-10
Quantity
per Reel
3,000
1,000
3,000
Branding
P1E
P1E
P1E
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. B
–3–
ADP3415
VCC
VCC
UVLO
V
UVLOTH
SD
BIAS
THERM
SD
THSD
BST
IN
DRVH
T
ON
DLY
DLY
R
DLY
VCC
R
DRVL
T
ON
DLY
DRVLSD
Q
S
GND
DRVL
Q2
SET
R CLR
Q
S
+
DRVH
C
BST
Q1
VTOK
BIAS
EN
D
BST
V
DCIN
SW
ADP3415
Figure 2. Functional Block Diagram
IN
DRVLSD
tpdl
DRVLSD
DRVL
tpdh
DRVLSD
Figure 3.
DRVLSD
Propagation Delay
–4–
REV. B
ADP3415
IN
tpdl
DRVL
DRVL
tpdl
DRVH
tf
DRVL
tpdh
DRVH
tr
DRVL
tpdh
DRVL
DRVH-SW
tr
DRVH
tf
DRVH
Figure 4. Switching Timing Diagram (Propagation Delay Referenced to 50%, Rise and Fall Time to 10% and 90% Points)
IN
t
SWTO
DRVL
CROWBAR
ACTION
SW
DRVH
Figure 5. Switching Waveforms–SW Node Failure Mode–DRVL Timeout
REV. B
–5–
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