Features ................................................................................................................................................................ 6
System Block Diagrams ...................................................................................................................................... 11
Core Signal Descriptions..................................................................................................................................... 14
MAC Address Register {0,1,2} (R/W), Set of Three ................................................................................... 28
Transmit and Receive Status (RO) ............................................................................................................ 28
VLAN Tag (RO).......................................................................................................................................... 28
GMII Management Register Access Control (R/W) ................................................................................... 29
GMII Management Access Data (R/W)...................................................................................................... 29
Multicast Tables (R/W), Set of Eight .......................................................................................................... 29
Chapter 4. IP Core Generation and Evaluation .................................................................................. 39
IP Core Generation in IPexpress ........................................................................................................................ 39
Licensing the IP Core................................................................................................................................. 39
Getting Started ........................................................................................................................................... 39
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG51_3.3, April 2015
2
Tri-Speed Ethernet MAC User’s Guide
Table of Contents
IPexpress-Created Files and Top Level Directory Structure...................................................................... 41
Instantiating the Core ................................................................................................................................. 42
IP Core Generation in Clarity Designer............................................................................................................... 43
Getting Started ........................................................................................................................................... 43
Clarity Designer Created Files and Top Level Directory Structure ............................................................ 45
IP Core Implementation ............................................................................................................................. 47
Regenerating/Recreating the IP Core ........................................................................................................ 48
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 48
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 48
Enabling Hardware Evaluation in Diamond:............................................................................................... 51
Updating/Regenerating the IP Core .................................................................................................................... 51
Regenerating an IP Core in Diamond ........................................................................................................ 51
Test Application Design ...................................................................................................................................... 52
The Test Logic Module............................................................................................................................... 53
The ORCAstra to Host Bus/USI module .................................................................................................... 53
The Register Interface Module................................................................................................................... 53
TSMAC Support Logic ............................................................................................................................... 53
Simulation of the Test Application.............................................................................................................. 53
Test Application Registers ......................................................................................................................... 55
ECP5 Family Data Sheet ............................................................................................................ 64
Revision History .................................................................................................................................................. 65
Appendix H. Resource Utilization ....................................................................................................... 67
Ordering Part Number................................................................................................................................ 67
Ordering Part Number................................................................................................................................ 67
Ordering Part Number................................................................................................................................ 68
Ordering Part Number................................................................................................................................ 68
IPUG51_3.3, April 2015
4
Tri-Speed Ethernet MAC User’s Guide
Chapter 1:
Introduction
This document provides technical information about the Lattice 10/100/1G Tri-Speed Ethernet Media Access Con-
troller (TSMAC) IP core.
The TSMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet
network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3
IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC
extracts the different components of a frame and transfers them to higher applications through the FIFO interface.
The TSMAC IP core comes with the following documentation and files:
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core
Quick Facts
Table 1-1 gives quick facts about the TSMAC IP core.
Table 1-1. TSMAC IP Core Quick Facts
TSMAC IP Configuration
Across All IP Configurations (Classic, Gigabit, SGMII, MIIM)
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