IDT71V433 datasheet, PDF - EEWORLD Datasheet

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IDT71V433: Description32K x 32 3.3V Synchronous SRAM Flow-Through Outputs; File Size263KB，19 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT71V433 Overview

32K x 32 3.3V Synchronous SRAM Flow-Through Outputs

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32K x 32

3.3V Synchronous SRAM

Flow-Through Outputs

Features

32K x 32 memory configuration

Supports high performance system speed:

Commercial and Industrial:

— 11 11ns Clock-to-Data Access (50MHz)

— 12 12ns Clock-to-Data Access (50MHz)

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Single 3.3V power supply (+10/-5%)

Packaged in a JEDEC Standard 100-pin rectangular plastic

thin quad flatpack (TQFP).

IDT71V433

Description

The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-

nized as 32K x 32 with full support of various processor interfaces

including the Pentium™ and PowerPC™. The flow-through burst archi-

tecture provides cost-effective 2-1-1-1 performance for processors up to

50 MHz.

The IDT71V433 SRAM contains write, data-input, address and

control registers. There are no registers in the data output path (flow-

through architecture). Internal logic allows the SRAM to generate a

self-timed write based upon a decision which can be left until the

extreme end of the write cycle.

The burst mode feature offers the highest level of performance to

the system designer, as the IDT71V433 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from

the array after a clock-to-data access time delay from the rising clock

edge of the same cycle. If burst mode operation is selected (ADV=LOW),

the subsequent three cycles of output data will be available to the

user on the next three rising clock edges. The order of these three

addresses will be defined by the internal burst counter and the

LBO

input pin.

The IDT71V433 SRAM utilizes IDT's high-performance 3.3V

CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP).

Pin Description

–A

BWE

–BW

CLK

ADV

ADSC

ADSP

LBO

I/O

–I/O

, V

DDQ

, V

SSQ

Address Inputs

Chip Enable

Chips Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock Input

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input/Output

Co re and I/O Power Supply (3.3V)

Array Ground, I/O Ground

Input

I/O

Power

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

3729 tbl 01

Pentium is a trademark of Intel Corp.

PowerPC is a trademark of International Business Machines, Inc.

AUGUST 2001

DSC-3729/04

IDT71V433 Related Products

	IDT71V433	71V433S11PF	71V433S12PF	71V433S11PFI	71V433S12PFI	IDT71V433S11PF	IDT71V433S12PF	IDT71V433S11PFI	IDT71V433S12PFI
Description	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs	32K x 32 3.3V Synchronous SRAM Flow-Through Outputs

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