74LVCZ161284A
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
WITH ERROR-FREE POWER-UP
I
I
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HIGH SPEED: t
PD
= 9ns (MAX.) at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
=20µA (MAX) at V
CC
=3.6V T
A
=85°C
TTL COMPATIBLE INPUTS
V
IH
=2V (MIN) V
IL
=0.8(MAX)
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 3.0V to 3.6V
A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
AUTO POWER-UP FEATURE TO PREVENT
PRINTER ERRORS
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
TRANSLATION CAPABILITY ALLOW
OUTPUTS ON CABLE SIDE TO INTERFACE
WITH 5V SIGNAL
PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
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DESCRIPTION
The 74LVCZ161284A contains eight high speed
non inverting bidirectional buffers and eleven
control/status non-inverting buffers with open
drain outputs fabricated in silicon gate C
2
MOS
technology. It’s intended to provide a standard
signaling method for a bi-direction parallel
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. The Y output (Y9-Y13) stay
in the high state after power-on until an associated
input A9-A13) goes high. When an associated
input goes high, all Y outputs are active, and non
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T&R
74LVCZ161284ATTR
July 2005
74LVCZ161284A
inverting signals of the associated inputs are
driven through Y outputs. This special feature
prevents printer system errors caused by
deasserting the BUSY signal in the cable at
LOGIC DIAGRAM
power-on.
It is available in the commercial temperature
range.
NOTE A:
NOTE B:
NOTE C:
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ACTIVE INPUT DETECTION CIRCUIT
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The PMOS transistors prevent backdriving current from the signal pins to V
CC/CABLE
when V
CC/CABLE
is open or at GND. The
PMOS transistor is turned off when the associated driver is in the low state.
The PMOS transistor prevents backdriving current from the signal pins to V
CC/CABLE
when V
CC/CABLE
is open or at GND.
Active input detection circuit forces Y9-Y13 to the low state after power-on until one of the A9-A13 goes high. See below.
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2/12
74LVCZ161284A
PIN DESCRIPTION
PIN N°
1
2, 3, 4, 5, 6
8, 9, 11, 12, 13, 14, 16, 17
19
20, 21, 22, 23
24
25
29, 28, 27, 26
30
41, 40, 38, 37, 36, 35, 33, 32
47, 46, 45, 44, 43
48
10, 15, 34, 39
7, 18
31, 42
SYMBOL
HD
A9 to A13
A1 to A8
PLI
A14 to A17
HLO
HLI
C14 to C17
PLO
B1 to B8
Y9 to Y13
DIR
GND
V
CC
V
CC/CABLE
NAME AND FUNCTION
High Drive Enable Input
Side A Input
Side A Input or Output
Peripheral Logic Input
Side A Output
Host Logic Output
Host Logic Input
Side Cable Output
Peripheral Logic Output
Side Cable Input or Output
Side Cable Output
Direction Control Input
Ground (0V)
Positive Supply Voltage
Cable Power Supply
TRUTH TABLE
INPUT
DIR
L
L
H
H
HD
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L
H
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OUTPUT
OUTPUT
Y9-Y13 and PLO Open
Drain
Y9-Y13 and PLO Totem
Pole
B1-B8 Y9-Y13 and PLO
Open Drain
B1-B8 Y9-Y13 and PLO
Totem Pole
B1-B8 Data to A1-A8
A9-A13 Data to Y9-Y13
C14-C17 Data to A14-A17
A1-A8 Data to B1-B8
A9-A13 Data to Y9-Y13
C14-C17 Data to A14-A17
3/12
74LVCZ161284A
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
CCcable
V
IA
V
IB
V
IBp
V
OA
V
OB
V
OBp
I
IK
I
OK
I
O
Supply Voltage
Cable Supply Voltage (must be
≥
V
CC
)
DC Input Voltage A1-A13, PL
IN
, DIR, HD
IN
DC Input Voltage B1-B8, C14-C17, HL
IN
DC Input Voltage B1-B8, C14-C17, HL
IN
(40ns transient)
DC Output Voltage A1-A8, A14-A17, HL
IN
DC Output Voltage B1-B8, Y9-Y13, PL
IN
DC Output Voltage B1-B8, Y9-Y13, PL
IN
(40ns transient)
DC Input Diode Current DIR, HD A9-A13, PL
IN
C14-C17
DC Output Diode Current
DC Output Current
A1-A8, A14-A17, HL
IN
B1-B8, Y9-Y13, PL
IN
A1-A8, HL
IN
B1-B8, Y9-Y13
PL
O
= LOW
PL
O
= HIGH
I
CC
or I
GND
DC V
CC
or Ground Current per Supply Pin
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +4.6
-0.5 to +7.0
-0.5 to +V
CC
+ 0.5
-0.5 to +5.5
-2 to +7
-0.5 to +V
CC
+ 0.5
-0.5 to +5.5
-2 to +7
- 20
±
50
Unit
V
V
V
V
V
V
V
Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not
implied
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
CCcable
V
I
V
O
T
op
Supply Voltage
Input Voltage
Cable Supply Voltage
b
O
et
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Open Drain Output Voltage
Operating Temperature
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Parameter
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P
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- 50
±
25
84
±
50
-50
±
200
300
ct
s)
(
V
mA
mA
mA
mA
°C
°C
-65 to +150
Value
3.0 to 3.6
3.0 to 5.5
0 to V
CC
0 to 5.5
-40 to 85
Unit
V
V
V
V
°C
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74LVCZ161284A
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
V
CCcable
(V)
Value
-40 to 85 °C
Min.
2
2.3
3.0
to
3.6
3.0
to
5.5
2.6
0.8
0.8
1.6
3.0
3.0
3.0
3.0
3.15
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
4.5
3.15
3.0
3.0
3.0
4.5
I
O
=-50µA
I
O
=-4mA
I
O
=-14mA
I
O
=-14mA
I
O
=-500µA
2.8
V
V
Max.
Unit
V
IH
High Level
Input Voltage
An, Bn, PL
IN
, DIR, HD
Cn
HL
IN
An, Bn, PL
IN
, DIR, HD
Cn
HL
IN
V
IL
Low Level
Input Voltage
V
OH
High Level
An, HL
Output Voltage
Bn, Yn
Bn, Yn
PL
V
OL
Low Level
An, HL
Output Voltage
Bn, Yn
Bn, Yn
PL
PL
I
I
Input Current
Cn
All input except B or C
I
CC
I
OZ
Quiescent Supply Current
High
Impedance
Output
Leakage
Current
Power Off
Leakage
Current
Input
Hysteresis
b
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OFF
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P
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Bn
Cn
HL
IN
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(s
t
3.0
3.6
3.6
b
O
3.0
4.5
3.6
3.6
5.0
5.0
5.0
3.6
5.0
3.6
5.0
5.0
5.0
5.0
5.0
5.0
5.0
so
te
le
I
O
=50µA
I
O
=4mA
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2.4
2.0
2.23
3.1
s)
t(
V
0.2
0.4
0.8
0.77
0.95
0.90
50
-3.5
±
1
0.8
45
20
-3.5
±
20
-3.5
100
10
0.4
0.8
0.2
V
Ω
Ω
µA
mA
µA
mA
µA
mA
µA
mA
µA
µA
V
I
O
=14mA
I
O
=14mA
I
O
=84mA
I
O
=84mA
V
I
= V
CC
3.6
V
I
=GND (Pull-up res)
V
I
= V
CC
or GND
V
I
= V
CC
I
O
=0
V
I
=GND (12xPull-up)
V
O
= V
CC
V
O
=GND (Pull-up res)
V
O
= V
CC
or GND
V
O
=GND (Pull-up res)
V
I
or V
O
= 0 to 7V
V
I
or V
O
= 0 to 7V
3.6
3.6
3.6
3.6
3.6
0
0
3.3
3.3
3.3
3.3
3.3
A1-A8
Open Drain Y Output
B, Y output (to V
CC
)
B, Y output (to GND)
V
hys
An, Bn, PL
IN
, DIR, HD
Z
O
R
P
Output
Impedance
Pull-up
Resistance
B1-B8, Y9-Y13
B1-B8, Y9-Y13,
C14-C17
V
B
= V
OH
V
B
= V
OH
30
1150
55
1650
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