SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte
FIFOs
Rev. 4 — 8 June 2010
Product data sheet
1. General description
The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel (16 mode) or Motorola (68 mode) interface.
The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C554B/554DB. Some of these added features are
the 16-byte receive and transmit FIFOs, four receive trigger levels. The
SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the
HVQFN48 package.) On-board status registers provide the user with error indications,
operational status, and modem interface control. System interrupts may be tailored to
meet user requirements. An internal loopback capability allows on-board diagnostics.
The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, LQFP80, and HVQFN48 packages.
On the HVQFN48 package only, channel C has all the modem pins. Channels A and B
have only RTSn and CTSn pins and channel D does not have any modem pin.
2. Features and benefits
4 channel UART
5 V, 3.3 V and 2.5 V operation
Industrial temperature range (−40
°C
to +85
°C)
The SC16C554B is pin and software compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554
The SC16C554DB is pin and software compatible with ST16C554D, and software
compatible with ST16C454/554, ST16C554, TL16C554
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
5 V tolerant on input only pins
1
16-byte transmit FIFO
16-byte receive FIFO with error flags
Programmable auto-RTS and auto-CTS
In auto-CTS mode, CTS controls transmitter
In auto-RTS mode, RX FIFO contents and threshold control RTS
1.
For data bus pins D7 to D0, see
Table 24 “Limiting values”.
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Automatic hardware flow control (RTS/CTS)
Software selectable baud rate generator
Four selectable Receive FIFO interrupt trigger levels
Standard modem interface
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Fully programmable character formatting:
5-bit, 6-bit, 7-bit, or 8-bit characters
Even, odd, or no-parity formats
1, 1
1
∨
2
, or 2-stop bit
Baud generation (DC to 5 Mbit/s)
False start-bit detection
Complete status reporting capabilities
3-state output TTL drive capabilities for bidirectional data bus and control bus
Line break generation and detection
Internal diagnostic capabilities:
Loopback controls for communications link fault isolation
Prioritized interrupt system controls
Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
3. Ordering information
Table 1.
Ordering information
Package
Name
SC16C554BIB64
SC16C554BIB80
SC16C554BIBM
SC16C554BIBS
SC16C554DBIA68
SC16C554DBIB64
LQFP64
LQFP80
LQFP64
HVQFN48
PLCC68
LQFP64
Description
plastic low profile quad flat package; 64 leads; body 10
×
10
×
1.4 mm
plastic low profile quad flat package; 80 leads; body 12
×
12
×
1.4 mm
plastic low profile quad flat package; 64 leads; body 7
×
7
×
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6
×
6
×
0.85 mm
plastic leaded chip carrier; 68 leads
plastic low profile quad flat package; 64 leads; body 10
×
10
×
1.4 mm
Version
SOT314-2
SOT315-1
SOT414-1
SOT778-3
SOT188-2
SOT314-2
Type number
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
2 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
4. Block diagram
SC16C554B/554DB
TRANSMIT
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TXA to TXD
D0 to D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA to RXD
A0 to A2
CSA to CSD
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
16/68
DTRA to DTRD
RTSA to RTSD
INTA to INTD
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA to CTSD
RIA to RID
CDA to CDD
DSRA to DSRD
INTSEL
002aaa877
XTAL1 XTAL2
CLKSEL
Fig 1.
Block diagram of SC16C554B/554DB (16 mode)
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
3 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
SC16C554B/554DB
TRANSMIT
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TXA to TXD
D0 to D7
R/W
RESET
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA to RXD
A0 to A4
CS
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
16/68
DTRA to DTRD
RTSA to RTSD
IRQ
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA to CTSD
RIA to RID
CDA to CDD
DSRA to DSRD
002aaa878
XTAL1 XTAL2
CLKSEL
Fig 2.
Block diagram of SC16C554B/554DB (68 mode)
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
4 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5. Pinning information
5.1 Pinning
5.1.1 PLCC68
65 INTSEL
GND
DSRA 10
CTSA 11
DTRA 12
V
CC
13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
CDB 27
RIB 28
RXB 29
V
CC
30
n.c. 31
A2 32
A1 33
A0 34
XTAL1 35
XTAL2 36
RESET 37
RXRDY 38
TXRDY 39
GND 40
RXC 41
RIC 42
CDC 43
61 CDD
60 DSRD
59 CTSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 V
CC
46 DTRC
45 CTSC
44 DSRC
002aaa879
© NXP B.V. 2010. All rights reserved.
CDA
63 RXD
RXA
64 V
CC
SC16C554DBIA68
16 mode
Fig 3.
Pin configuration for PLCC68 (16 mode)
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 4 — 8 June 2010
62 RID
RIA
D7
D6
D5
D4
D3
68 D2
67 D1
66 D0
9
8
7
6
5
4
3
2
1
5 of 58
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