ISL70001SRHQF datasheet, PDF - EEWORLD Datasheet

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ISL70001SRHQF: DescriptionSwitching Voltage Regulators RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR, CLASS Q, FP; CategoryPower/power management The power supply circuit; File Size630KB，21 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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ISL70001SRHQF Overview

Switching Voltage Regulators RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR, CLASS Q, FP

ISL70001SRHQF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	QFP
package instruction	QFP, QFL48,.55SQ,40
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	OPERATES IN ADJUSTABLE MODE FROM 0.8V TO 4.675V
Analog Integrated Circuits - Other Types	SWITCHING REGULATOR
control mode	CURRENT-MODE
Control Technology	PULSE WIDTH MODULATION
Maximum input voltage	5.5 V
Minimum input voltage	3 V
Nominal input voltage	3.3 V
JESD-30 code	S-CQFP-G48
JESD-609 code	e4
length	14.355 mm
Number of functions	1
Number of terminals	48
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Maximum output current	6 A
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP
Encapsulate equivalent code	QFL48,.55SQ,40
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.43 mm
surface mount	YES
Switch configuration	BUCK
Maximum switching frequency	1000 kHz
Temperature level	MILITARY
Terminal surface	Gold (Au)
Terminal form	GULL WING
Terminal pitch	1.02 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14.355 mm
Base Number Matches	1

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DATASHEET

ISL70001SEH, ISL70001SRH

Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator

The

ISL70001SEH, ISL70001SRH

are radiation hardened and

SEE hardened high efficiency monolithic synchronous buck

regulators with integrated MOSFETs. This single chip power

solution operates over an input voltage range of 3V to 5.5V

and provides a tightly regulated output voltage that is

externally adjustable from 0.8V to ~85% of the input voltage.

Output load current capacity is 6A for T

< +145°C

High integration and class leading radiation tolerance makes

the ISL70001SEH, ISL70001SRH ideal choices to power

many of today’s small form factor applications. Two devices

can be synchronized to provide a complete power solution for

large scale digital ICs, like field programmable gate arrays

(FPGAs) that require separate core and I/O voltages.

In applications where the ENABLE input is tied high to PVIN we

recommend that the input voltage ramp rate be equal to or

greater than 10V/ms. This is to prevent unwanted voltage from

prematurely appearing on the output.

For a PVIN voltage that has a slower ramp rate or is stepped up

we recommend use of the

ISL70001ASEH.

Ensuring that the

ENABLE input is held low until the chosen VINPOR is satisfied

will prevent this ‘false start’.

FN7956

Rev 3.00

February 22, 2014

Features

• ±1% reference voltage over line, load, temperature and

radiation

• Current mode control for excellent dynamic response

• Full Mil-temp range operation (T

= -55°C to +125°C)

• High efficiency >90%

• Fixed 1MHz operating frequency

• Available in a thermally enhanced heatsink package - R48.B

• Operates from 3V to 5.5V supply

• Adjustable output voltage

- Two external resistors set V

OUT

from 0.8V to ~85% of V

• Bidirectional SYNC pin allows two devices to be

synchronized 180° out-of-phase

• Starts into prebiased load

• Power-good output voltage monitor

• Adjustable analog soft-start

• Input undervoltage, output undervoltage and output

overcurrent protection

• Electrically screened to DLA SMD

5962-09225

• QML qualified per MIL-PRF-38535 requirements

• EH version is wafer-by-wafer acceptance tested for ELDRS

• Radiation hardness

- Total dose [50-300rad(Si)/s] . . . . . . . . . 100krad(Si) (min)

- Total dose [<10mrad(Si)/s] . . . . . . . . . . . .50krad(Si) (min)

• SEE hardness

- SEL and SEB LET

eff

. . . . . . . . . . . 86.4MeV/mg/cm

(min)

- SEFI X-section (LET

eff

= 86.4MeV/mg/cm

) 1.4 x 10

-6

(max)

- SET LET

eff

(<1 pulse perturbation) 86.4MeV/mg/cm

(min)

Applications

• FPGA, CPLD, DSP, CPU core or I/O voltages

• Low-voltage, high-density distributed power systems

Related Literature

•

AN1518

ISL70001SRHEVAL1Z Evaluation Board,

•

Single Event Effects (SEE)

Testing of the ISL70001SRH

Synchronous Buck Regulator

•

Total Dose Testing

of the ISL70001SRH Hardened Point of

Load Regulator

ISL70001SEH

SYNCH

CORE

EFFICIENCY (%)

5V SUPPLY

ISL75051SEH

AUX

RAD TOLERANT

FPGA

ISL70001SEH

SYNCH

I/O

LOAD CURRENT (A)

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. EFFICIENCY 5V INPUT TO 3.3V OUTPUT, T

= +25°C

FN7956 Rev 3.00

February 22, 2014

Page 1 of 21

ISL70001SEH, ISL70001SRH

Pin Descriptions

PIN NUMBER

1, 2, 27, 28, 29, 30,

37, 38, 39, 40, 47,

3, 26, 31, 36, 41,

PIN NAME

PGNDx

DESCRIPTION

These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins

directly to the ground plane. These pins should also connect to the negative terminals of the input and output

capacitors. Locate the input and output capacitors as close as possible to the IC.

These pins are the outputs of the corresponding internal power blocks and should be connected to the output

filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize

voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The

Schottky diode should be located as close as possible to the IC.

These pins are the power supply inputs to the corresponding internal power blocks. These pins must be

connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly

to PGNDx with ceramic capacitors located as close as possible to the IC.

This pin is the synchronization I/O for the IC. When configured as an output (Master mode), this pin drives the

SYNC input of another ISL70001SEH, ISL70001SRH. When configured as an input (Slave mode), this pin

accepts the SYNC output from another ISL70001SEH, ISL70001SRH or an external clock. Synchronization of

the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the

clock must be SEE hardened and the frequency must be within the range of 1MHz ±20%.

This pin is the Master/Slave input for selecting the direction of the bidirectional SYNC pin. For SYNC = Output

(Master mode), connect this pin to DVDD. For SYNC = Input (Slave mode), connect this pin to DGND.

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.

This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.

This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.

This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when the output

voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,

independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to

DGND with a 10nF ceramic capacitor to mitigate SEE.

This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output

ramp time in accordance with

Equation 1:



REF



(EQ. 1)

LXx

4, 5, 24, 25, 32, 33,

34, 35, 42, 43, 44,

PVINx

SYNC

M/S

ZAP

TDI

TDO

PGOOD

Where:

= Soft-start output ramp time

= Soft-start capacitor

REF

= Reference voltage (0.6V typical)

= Soft-start charging current (23µA typical)

Soft-start time is adjustable from approximately 2ms to 200ms.

The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.

13, 14

DVDD

These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the

IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter

components as close as possible to the IC.

These pins are the digital ground associated with the internal digital control circuitry. Connect these pins

directly to the ground plane.

These pins are the analog ground associated with the internal analog control circuitry. Connect these pins

directly to the ground plane. Reference

“Metallization Mask Layout” on page 17,

pad 13 is labeled PGND and

is pin 17 on the packaged device. These 2 pads are to be connected together when using the die product.

This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω

resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.

This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor

located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or

sinking) is available from this pin.

15, 16

17, 18

DGND

AGND

AVDD

REF

FN7956 Rev 3.00

February 22, 2014

Page 4 of 21

ISL70001SRHQF Related Products

	ISL70001SRHQF	ISL70001SEHVFE	ISL70001SRHF/PROTO	ISL70001SEHVF
Description	Switching Voltage Regulators RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR, CLASS Q, FP	Switching Voltage Regulators RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR, CLS V, EP-FP,	Switching regulator RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR, PROTO, FP	Switching regulator RADIATION HARDENED SYNCHRONOUS BUCK REGULATOR,CLS V,FP,HDR/L
Is it Rohs certified?	conform to	-	conform to	conform to
Maker	Renesas Electronics Corporation	-	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	QFP	-	QFP	QFP
package instruction	QFP, QFL48,.55SQ,40	-	QFF,	QFF, QFL48,.55SQ,40
Contacts	48	-	48	48
Reach Compliance Code	compliant	-	compliant	compliant
ECCN code	EAR99	-	USML XV(E)	EAR99
Other features	OPERATES IN ADJUSTABLE MODE FROM 0.8V TO 4.675V	-	OPERATES IN ADJUSTABLE MODE FROM 0.8V TO 4.675V	OPERATES IN ADJUSTABLE MODE FROM 0.8V TO 4.675V
Analog Integrated Circuits - Other Types	SWITCHING REGULATOR	-	SWITCHING REGULATOR	SWITCHING REGULATOR
control mode	CURRENT-MODE	-	CURRENT-MODE	CURRENT-MODE
Control Technology	PULSE WIDTH MODULATION	-	PULSE WIDTH MODULATION	PULSE WIDTH MODULATION
Maximum input voltage	5.5 V	-	5.5 V	5.5 V
Minimum input voltage	3 V	-	3 V	3 V
Nominal input voltage	3.3 V	-	3.6 V	3.6 V
JESD-30 code	S-CQFP-G48	-	S-CQFP-F48	S-CQFP-F48
length	14.355 mm	-	14.355 mm	14.355 mm
Number of functions	1	-	1	1
Number of terminals	48	-	48	48
Maximum operating temperature	125 °C	-	125 °C	125 °C
Minimum operating temperature	-55 °C	-	-55 °C	-55 °C
Maximum output current	6 A	-	6 A	6 A
Package body material	CERAMIC, METAL-SEALED COFIRED	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP	-	QFF	QFF
Package shape	SQUARE	-	SQUARE	SQUARE
Package form	FLATPACK	-	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	3.43 mm	-	3.43 mm	3.43 mm
surface mount	YES	-	YES	YES
Switch configuration	BUCK	-	BUCK	BUCK
Maximum switching frequency	1000 kHz	-	1200 kHz	1200 kHz
Temperature level	MILITARY	-	MILITARY	MILITARY
Terminal form	GULL WING	-	FLAT	FLAT
Terminal pitch	1.02 mm	-	1.016 mm	1.016 mm
Terminal location	QUAD	-	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	14.355 mm	-	14.355 mm	14.355 mm

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