FemtoClock
®
NG Crystal-to-3.3V
LVPECL Frequency Synthesizer
843N252-45
Data Sheet
General Description
The 843N252-45 is a 1 LVPECL and 1 LVCMOS output Synthesizer
optimized to generate Ethernet reference clock frequencies. The
device uses IDT’s fourth generation FemtoClock
®
NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. Using a 25MHz parallel resonant
crystal, the following frequencies can be generated: 156.25MHz and
125MHz. With a very low phase noise VCO it is targeted to achieve
0.4ps or lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The 843N252-45 is packaged in a small 16-pin
TSSOP package.
Features
•
•
•
•
•
•
•
•
•
•
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Fourth generation FemtoClock
®
Next Generation (NG) technology
One differential 3.3V LVPECL output and one LVCMOS/LVTTL
output
Crystal oscillator interface designed for a 25MHz parallel resonant
crystal
A 25MHz crystal generates output frequencies of: 156.25MHz and
125MHz
VCO frequency: 625MHz
RMS Phase Jitter @ 156.25MHz, (12kHz – 20MHz) using a
25MHz crystal: 0.33ps (typical)
RMS Phase Jitter @ 125MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.39ps (typical)
Power supply noise rejection PSNR: -60dB (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_ENA
Pullup
Pin Assignment
CLK_ENA
V
EE
QA
V
CCOA
nc
nc
V
CCA
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_ENB
V
EE
QB
nQB
V
CC
XTAL_IN
XTAL_OUT
V
EE
XTAL_IN
XTAL_OUT
25MHz
OSC
PFD
&
LPF
FemtoClock
®
NG
VCO
625MHz
÷5
QA
QB
÷4
nQB
Feedback Divider
÷25
CLK_ENB
Pullup
843N252-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
©2016 Integrated Device Technology, Inc
1
Revision A April 20, 2016
843N252-45 Data Sheet
Table 1. Pin Descriptions
Number
1
2, 9, 15
3
4
5, 6
7
8, 12
10
11
13, 14
16
Name
CLK_ENA
V
EE
QA
V
CCOA
nc
V
CCA
V
CC
XTAL_OUT
XTAL_IN
nQB, QB
CLK_ENB
Input
Power
Output
Power
Unused
Power
Power
Input
Output
Input
Pullup
Type
Pullup
Description
Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3A.
Negative supply pins.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pin for QA output.
No connect.
Analog supply pin.
Power supply pin.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Differential output pair. LVPECL interface levels.
Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Output Impedance
QA
V
CCO_A
= 3.465V
V
CC
= V
CCO_A
= 3.465V
Test Conditions
Minimum
Typical
4
7
51
15
Maximum
Units
pF
pF
k
Function Tables
Table 3A. CLK_ENA Function Table
Input
CLK_ENA
0
1
Outputs
QA
High-Impedance
Active
Table 3B. CLK_ENB Function Table
Input
CLK_ENB
0
1
QB
HIGH
Active
Outputs
nQB
LOW
Active
©2016 Integrated Device Technology, Inc
2
Revision A April 20, 2016
843N252-45 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to V
CC
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCOA
+ 0.5V
50mA
100mA
94.8C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCOA
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCOA
I
CCA
I
EE
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Voltage
Analog Supply Current
Power Supply Current
No Load
Test Conditions
Minimum
3.135
V
CC
– 0.14
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
14
124
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCOA
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_ENA,
CLK_ENB
CLK_ENA,
CLK_ENB
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CCOA
= 3.3V ± 5%
V
CCOA
= 3.3V ± 5%
-150
2.3
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
to V
CCOA
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
©2016 Integrated Device Technology, Inc
3
Revision A April 20, 2016
843N252-45 Data Sheet
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.55
Typical
Maximum
V
CC
– 0.75
V
CC
– 1.5
1.05
Units
V
V
V
NOTE 1: Output termination with 50 to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
AC Electrical Characteristics
Table 6. AC Characteristics,
V
CC
= V
CCOA
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
QA
QB, nQB
QA
QB, nQB
125MHz, Integration Range:
12kHz – 20MHz
156.25MHz, Integration Range:
12kHz – 20MHz
From DC to 10MHz
20% to 80%
20% to 80%
250
150
47
48
Test Conditions
Minimum
Typical
125
156.25
0.39
0.33
-60
500
300
53
52
Maximum
Units
MHz
MHz
ps
ps
dB
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter
(Random); NOTE 1
PSNR
t
R
/ t
F
odc
Power Supply Noise Reduction
Output Rise/Fall Time
Output Duty Cycle
QA
QB, nQB
QA
QB, nQB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Using a 25MHz, 12pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plots.
©2016 Integrated Device Technology, Inc
4
Revision A April 20, 2016
843N252-45 Data Sheet
Typical Phase Noise at 125MHz
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.39ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.33ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
5
Revision A April 20, 2016
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