NB4N11MDTG datasheet, PDF - EEWORLD Datasheet

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NB4N11MDTG: DescriptionClock Buffer MLTLVL IN-CML RECBUF; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size216KB，11 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NB4N11MDTG Overview

Clock Buffer MLTLVL IN-CML RECBUF

NB4N11MDTG Parametric

Parameter Name	Attribute value
Brand Name	ON Semiconductor
Is it lead-free?	Lead free
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	LEAD FREE, PLASTIC TSSOP-8
Contacts	8
Manufacturer packaging code	948R-02
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	1 week
Samacsys Description	NULL
maximum delay	0.6 ns
Interface integrated circuit type	PECL TO CML TRANSLATOR
JESD-30 code	S-PDSO-G8
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	3
Number of digits	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-COLLECTOR
Output latch or register	NONE
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP8,.19
Package shape	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3 mm

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NB4N11M

3.3 V 2.5 Gb/s Multi Level

Clock/Data Input to CML

Receiver/ Buffer/ Translator

Description

T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1

−t

−2

c l o c k / d a t a

distribution/translation chip with CML output structure, targeted for

high−speed clock/data applications. The device is functionally

equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device

produces two identical differential output copies of clock or

data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,

NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and

other clock/data distribution applications.

Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS

(See Table 5). The CML outputs are 16 mA open collector

(See Figure 18) which requires resistor (R

) load path to V

termination voltage. The open collector CML outputs must be

terminated to V

at power up. Differential outputs produces

current–mode logic (CML) compatible levels when receiver loaded

with 50

or 25

loads connected to 1.8 V, 2.5 V or 3.3 V supplies

(see Figure 19). This simplifies device interface by eliminating a need

for coupling capacitors.

The device is offered in a small 8−pin TSSOP package.

Application notes, models, and support documentation are available

at www.onsemi.com.

Features

http://onsemi.com

MARKING

DIAGRAM*

TSSOP−8

DT SUFFIX

CASE 948R

E11M

ALYWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

•

Maximum Input Clock Frequency > 2.5 GHz

Maximum Input Data Rate > 2.5 Gb/s

Typically 1 ps of RMS Clock Jitter

Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R

= 25

420 ps Typical Propagation Delay

150 ps Typical Rise and Fall Times

Operating Range: V

= 3.0 V to 3.6 V with V

= 0 V and

= 1.8 V to 3.6 V

•

Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

•

These are Pb−Free Devices*

Figure 1. Functional Block Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

November, 2005

−

Rev. 1

Publication Order Number:

NB4N11M/D

NB4N11MDTG Related Products

	NB4N11MDTG	NB4N11MDTR2G
Description	Clock Buffer MLTLVL IN-CML RECBUF	Clock Buffer MLTLVL IN-CML RECBUF
Brand Name	ON Semiconductor	ON Semiconductor
Is it lead-free?	Lead free	Lead free
Maker	ON Semiconductor	ON Semiconductor
Parts packaging code	SOIC	SOIC
package instruction	LEAD FREE, PLASTIC TSSOP-8	TSSOP, TSSOP8,.19
Contacts	8	8
Manufacturer packaging code	948R-02	948R-02
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Factory Lead Time	1 week	1 week
maximum delay	0.6 ns	0.6 ns
Interface integrated circuit type	PECL TO CML TRANSLATOR	PECL TO CML TRANSLATOR
JESD-30 code	S-PDSO-G8	S-PDSO-G8
JESD-609 code	e3	e3
length	3 mm	3 mm
Humidity sensitivity level	3	3
Number of digits	1	1
Number of functions	1	1
Number of terminals	8	8
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	OPEN-COLLECTOR	OPEN-COLLECTOR
Output latch or register	NONE	NONE
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP8,.19	TSSOP8,.19
Package shape	SQUARE	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	NOT SPECIFIED
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin (Sn)	Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	NOT SPECIFIED
width	3 mm	3 mm

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