NB4N11M
3.3 V 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/ Buffer/ Translator
Description
T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1
−t
o
−2
c l o c k / d a t a
distribution/translation chip with CML output structure, targeted for
high−speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (R
L
) load path to V
TT
termination voltage. The open collector CML outputs must be
terminated to V
TT
at power up. Differential outputs produces
current–mode logic (CML) compatible levels when receiver loaded
with 50
W
or 25
W
loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
The device is offered in a small 8−pin TSSOP package.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
http://onsemi.com
MARKING
DIAGRAM*
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
E11M
ALYWG
G
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
D
D
Q1
Q1
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.5 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R
L
= 25
W
420 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V and
V
TT
= 1.8 V to 3.6 V
•
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
•
These are Pb−Free Devices*
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
November, 2005
−
Rev. 1
1
Publication Order Number:
NB4N11M/D
NB4N11M
Q0
1
8
V
CC
Q0
2
7
D
Q1
3
6
D
Q1
4
5
V
EE
Figure 2. Pinout
(Top View)
and Logic Diagram
Table 1. Pin Description
Pin
1
Name
Q0
I/O
CML Output
Description
Noninverted differential output. Typically receiver terminated with 50
W
resistor to V
TT
. Open collector CML outputs must be terminated to V
TT
at
powerup.
Inverted differential output. Typically receiver terminated with 50
W
resistor
to V
TT
. Open collector CML outputs must be terminated to V
TT
at powerup.
Noninverted differential output. Typically receiver terminated with 50
W
resistor to V
TT
. Open collector CML outputs must be terminated to V
TT
at
powerup.
Inverted differential output. Typically receiver terminated with 50
W
resistor
to V
TT
. Open collector CML outputs must be terminated to V
TT
at powerup.
Negative supply voltage.
Inverted differential input.
Noninverted differential input.
Positive supply voltage.
2
3
Q0
Q1
CML Output
CML Output
4
5
6
7
8
Q1
V
EE
D
D
V
CC
CML Output
−
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
−
http://onsemi.com
2
NB4N11M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
8−TSSOP
Oxygen Index: 28 to 34
Value
> 1000 V
> 70 V
Level 1
UL 94 V−0 @ 0.125 in
197
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
O
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Output Voltage
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
1S2P (Note 2)
< 3 Sec @ 260°C
TSSOP−8
TSSOP−8
TSSOP−8
Minimum
Maximum
Condition 1
V
EE
=
−0.5
V
V
CC
= +0.5 V
V
EE
= 0 V
V
CC
= 0 V
V
I
= V
CC
+0.4 V
V
I
= V
EE
–0.4 V
Condition 2
Rating
4
−4
4
−4
V
EE
+ 600
V
CC
+ 400
−40
to +85
−65
to +150
190
130
41 to 44
265
Unit
V
V
V
V
mV
mV
°C
°C
°C/W
°C/W
°C/W
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB4N11M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs
V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
OH
V
OL
|V
OD
|
V
OH
V
OL
|V
OD
|
V
OH
V
OL
|V
OD
|
V
OH
V
OL
|V
OD
|
V
th
V
IH
V
IL
V
IHD
V
ILD
V
CMR
|V
ID
|
C
IN
Characteristic
Power Supply Current (Inputs and Outputs Open)
Min
Typ
25
Max
35
Unit
mA
R
L
= 50
W,
V
TT
= 3.6 V to 2.5 V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
−
60
V
TT
−
1100
640
V
TT
−
10
V
TT
−
800
780
V
TT
V
TT
−
640
1000
mV
mV
mV
R
L
= 25
W,
V
TT
= 3.6 V to 2.5 V
$5%
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
−
60
V
TT
−
550
320
V
TT
−
10
V
TT
−
400
390
V
TT
V
TT
−
320
500
mV
mV
mV
R
L
= 50
W,
V
TT
= 1.8 V
$5%
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
−
170
V
TT
−
1100
570
V
TT
−
10
V
TT
−
800
780
V
TT
V
TT
−
640
1000
mV
mV
mV
R
L
= 25
W,
V
TT
= 1.8 V
$5%
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
−
85
V
TT
−
500
285
V
TT
−
10
V
TT
−
400
390
V
TT
V
TT
−
320
500
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 14 and 16)
Input Threshold Reference Voltage Range (Note 5)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
V
EE
V
th
+ 100
V
EE
−
400
V
EE
V
EE
−
400
V
EE
100
1.5
V
CC
V
CC
+ 400
V
th
−
100
V
CC
+ 400
V
CC
−
100
V
CC
V
CC
−
V
EE
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 15 and 17)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage Magnitude (|V
IHD
−
V
ILD
|) (Note 7)
Input Capacitance (Note 7)
mV
mV
mV
mV
pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. CML outputs require R
L
receiver termination resistors to V
TT
for proper operation. Outputs must be connected through R
L
to V
TT
at power
up. The output parameters vary 1:1 with V
TT
.
4. Input parameters vary 1:1 with V
CC
.
5. V
th
is applied to the complementary input when operating in single−ended mode.
6. V
CMR
(MIN) varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
7. Parameter guaranteed by design and evaluation but not tested in production.
http://onsemi.com
4
NB4N11M
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V; (Note 8)
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (R
L
= 50
W)
f
in
≤
1 GHz
(See Figure 12)
f
in
≤
1.5 GHz
f
in
≤
2.5GHz
Output Voltage Amplitude (R
L
= 25
W)
f
in
≤
1 GHz
(See Figure 12)
f
in
≤
1.5 GHz
f
in
≤
2.5GHz
Maximum Operating Data Rate
Propagation Delay to Output Differential
@ 0.5 GHz
Duty Cycle Skew (Note 9)
Within Device Skew
Device to Device Skew (Note 13)
RMS Random Clock Jitter R
L
= 50
W
and
R
L
= 25
W
(Note 11)
f
in
= 750 MHz
f
in
= 1.5 GHz
f
in
= 2.5 GHz
Peak−to−Peak Data Dependent Jitter R
L
= 50
W
f
DATA
= 1.5 Gb/s
(Note 12)
f
DATA
= 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter R
L
= 25
W
f
DATA
= 1.5 Gb/s
(Note 12)
f
DATA
= 2.5 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times @ 0.5 GHz
(20%
−
80%)
Q, Q
100
150
300
Min
550
400
150
280
280
100
1.5
300
Typ
660
640
400
370
360
300
2.5
420
2
5
20
1
1
1
15
20
5
10
600
20
25
100
3
3
3
55
85
35
35
100
150
300
Max
Min
550
400
150
280
280
100
1.5
300
25°C
Typ
660
640
400
370
360
400
2.5
420
2
5
20
1
1
1
15
20
5
10
600
20
25
100
3
3
3
55
85
35
35
100
150
300
Max
Min
550
400
150
280
280
100
1.5
300
85°C
Typ
660
640
400
370
360
400
2.5
420
2
5
20
1
1
1
15
20
5
10
600
20
25
100
3
3
3
55
85
35
35
mV
ps
Max
Unit
mV
V
OUTPP
mV
f
DATA
t
PLH
,
t
PHL
t
SKEW
Gb/s
ps
ps
t
JITTER
ps
V
INPP
t
r
t
f
OUTPUT VOLTAGE AMPLITUDE (mV)
700
600
500
400
300
200
100
0
0.75
1
1.25 1.5
1.75
2
2.25 2.5 2.75
3
R
L
= 25
W
R
L
= 50
W
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All output loaded with an external R
L
= 50
W
and R
L
= 25
W
to V
TT
.
Outputs must be connected through R
L
to V
TT
at power up. Input edge rates 150 ps (20%
−
80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw−
and T
pw+
@ 0.5 GHz.
10. V
INPP
(MAX) cannot exceed V
CC
−
V
EE
. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 2
23
−1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.75
1
1.25 1.5
1.75
2
2.25 2.5
2.75
3
R
L
= 25
W
R
L
= 50
W
INPUT CLOCK FREQUENCY (GHz)
(V
CC
−
V
EE
= 3.3 V V
TT
= 3.3 V @ 255C V
in
= 100 mV)
INPUT CLOCK FREQUENCY (GHz)
(V
CC
−
V
EE
= 3.0 V V
TT
= 1.71 V @255C V
in
= 100 mV)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus Input Clock Frequency (f
IN
) at Ambient Temperature (Typical)
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
