HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
Preliminary
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
Single 3.3±0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (10.5mm x 8.3mm)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
•
•
Internal four banks operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
ORDERING INFORMATION
Part No.
HY5V26CF-6
HY5V26CF-K
HY5V26CF-H
HY5V26CF-8
HY5V26CF-P
HY5V26CF-S
HY5V26C(L/S)F-6
HY5V26C(L/S)F-K
HY5V26C(L/S)F-H
HY5V26C(L/S)F-8
HY5V26C(L/S)F-P
HY5V26C(L/S)F-S
Clock Frequency
166MHz
133MHz
133MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
Low power
125MHz
100MHz
100MHz
4Banks x 2Mbits
x16
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 0.9/Jul. 02
1
HY5V26C(L/S)F
BALL DESCRIPTION
BALL OUT
F2
F3
SYMBOL
CLK
CKE
TYPE
INPUT
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated,
the SDRAM will be one of the states among power down, suspend or
self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM
and LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:Controls output buffers in read mode and masks input
data in write mode
Data Input/Output:Multiplexed data input/output ball
G9
G7,G8
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
F8, F7, F9
F1, E8
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1
CS
BA0, BA1
A0 ~ A11
INPUT
INPUT
INPUT
RAS, CAS,
WE
UDQM,
LDQM
INPUT
INPUT
DQ0 ~ DQ15 I/O
VDD/VSS
SUPPLY
Power supply for internal circuits
Power supply for output buffers
No connection
VDDQ/VSSQ SUPPLY
NC
-
HY5V26C(L/S)F
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any ball relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
(T
A
=0 to 70°C)
Parameter
Power Supply Voltage
Input High voltage
Input Low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL
(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION
(T
A
=0 to 70°C, V
DD
=3.3
±
0.3V, V
SS
=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
C
L
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.9/Jul. 02
5
TI Technology Forum
京公网安备 11010802033920号
EEWORLD
