HY5PS1G421(L)M
HY5PS1G821(L)M
1Gb DDR2 SDRAM(DDP)
HY5PS1G421(L)M
HY5PS1G821(L)M
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Oct. 2005
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1HY5PS12421(L)M
HY5PS12821(L)M
Revision History
Revision No.
0.1
0.2
Initial Release
Changed IDD Spec.(IDD2P & IDD6)
Corrected typo, Removed 667 speed bin
History
Draft Date
Mar.2003
Feb. 2005
Oct. 2005
Remark
Preliminary
Preliminary
Rev. 0.2 / Oct. 2005
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1HY5PS12421(L)M
HY5PS12821(L)M
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.2.1 256M x4 DDR2 DDP Pin Configuration
1.2.2 128M x8 DDR2 DDP Pin Configuration
1.3 Pin Description
2. Functioanal Description
2.1 Simplified State Diagram
2.2 Functional Block Diagram
2.2.1 Functional Block Diagram(256M x4)
2.2.2 Functional Block Diagram(128M x8)
2.3 Basic Function & Operation of DDR2 SDRAM
2.3.1 Power up and Initialization
2.3.2 Programming the Mode and Extended Mode Registers
2.3.2.1 DDR2 SDRAM Mode Register Set(MRS)
2.3.2.2 DDR2 SDRAM Extended Mode Register Set
2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment
2.3.2.4 ODT(On Die Termination)
2.4 Bank Activate Command
2.5 Read and Write Command
2.5.1 Posted CAS
2.5.2 Burst Mode Operation
2.5.3 Burst Read Command
2.5.4 Burst Write Operation
2.5.5 Write Data Mask
2.6 Precharge Operation
2.7 Auto Precharge Operation
2.8 Refresh Commands
2.8.1 Auto Refresh Command
2.8.2 Self Refresh Command
2.9 Power Down
2.10 Asynchronous CKE Low Event
2.11 No Operation Command
2.12 Deselect Command
3.1 Command Truth Table
3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors
3.3 Data Mask Truth Table
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Condition
3. Truth Tables
4. Operating Conditions
Rev. 0.2 / Oct. 2005
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1HY5PS12421(L)M
HY5PS12821(L)M
5. AC & DC Operating Conditions
5.1 DC Operation Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
5.2 DC & AC Logic Input Levels
5.2.1 Input DC Logic Level
5.2.2 Input AC Logic Level
5.2.3 AC Input Test Conditions
5.2.4 Differential Input AC Logic Level
5.2.5 Differential AC output parameters
5.2.6 Overshoot / Undershoot Specification
5.3 Output Buffer Levels
5.3.1 Output AC Test Conditions
5.3.2 Output DC Current Drive
5.3.3 OCD default chracteristics
5.4 Default Output V-I Characteristics
5.4.1 Full Strength Default Pulldown Driver Characteristics
5.4.2 Full Strength Default Pullup Driver Chracteristics
5.4.3 Calibrated Output Driver V-I Characteristics
5.5 Input/Output Capacitance
6. IDD Specifications & Measurement Conditions
7. AC Timing Specifications
7.1 Timing Parameters by Speed Grade
7.2 General Notes for all AC Parameters
7.3 Specific Notes for dedicated AC parameters.
8.1 Package Dimension(x4, x8)
8 Package Dimensions
Rev. 0.2 / Oct. 2005
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1HY5PS12421(L)M
HY5PS12821(L)M
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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Dual Die Package( 512Mb DDR2 * 2)
VDD, VDDQ=1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 supported
Programmable additive latency 0, 1, 2, 3, 4 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal 4bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 60ball FBGA(x4/x8)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
HY5PS1G421(L)M-X*
HY5PS1G821(L)M-X*
Configuration Package
256Mx4
128Mx8
63Ball
Operating Frequency
Grade
-E3
-C4
tCK(ns)
5
3.75
CL
3
4
tRCD
3
4
tRP
3
4
Unit
Clk
Clk
Note:
-X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
Rev. 0.2 / Oct. 2005
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