HY57V283220T-55 datasheet, PDF

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HY57V283220T-55: Description4 Banks x 1M x 32Bit Synchronous DRAM; Categorystorage storage; File Size906KB，15 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V283220T-55 Overview

4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220T-55 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSSOP, TSSOP86,.46,20
Contacts	86
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	183 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G86
length	22.238 mm
memory density	134217728 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	86
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP86,.46,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.194 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.22 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	10.16 mm

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HY57V283220(L)T(P)/ HY5V22(L)F(P)

4 Banks x 1M x 32Bit Synchronous DRAM

Revision History

Revision No.

0.1

History

Defined Preliminary Specification

Modified FBGA Ball Configuration Typo.

Changed Functional Block Diagram from A10 to A11.

Changed V

min from 3.0V to 3.135V.

Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.

Insert t

AC2

Value.

Insdrt t

RAS

& CLK Value.

Remark

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Defined I

Spec.

Delited Preliminary.

Changed I

Spec.

133MHz Speed Added

Changed FBGA Package Size from 11x13 to 8x13.

1) Changed V

min from 3.135V to 3.0V.

2) Changed V

min from V

SSQ

-0.3V to -0.3V.

Modified of size erra. (Page15)

(Equation :

13.00

-> 13.00

0.10)

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.9 / July 2004

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