HY57V281620ALT-7 datasheet, PDF

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HY57V281620ALT-7: Description4 Banks x 2M x 16bits Synchronous DRAM; Categorystorage storage; File Size95KB，13 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V281620ALT-7 Overview

4 Banks x 2M x 16bits Synchronous DRAM

HY57V281620ALT-7 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e6
length	22.22 mm
memory density	134217728 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.24 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

HY57V281620ALT-7 Preview

HY57V281620A

4 Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V281620A is organized as 4banks of 2,097,152x16

HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by UDQM or LDQM

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

•

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

ORDERING INFORMATION

Part No.

HY57V281620AT-6

HY57V281620AT-7

HY57V281620AT-K

HY57V281620AT-H

HY57V281620AT-8

HY57V281620AT-P

HY57V281620AT-S

HY57V281620ALT-6

HY57V281620ALT-7

HY57V281620ALT-K

HY57V281620ALT-H

HY57V281620ALT-8

HY57V281620ALT-P

HY57V281620ALT-S

Clock Frequency

166MHz

143MHz

133MHz

125MHz

100MHz

166MHz

143MHz

133MHz

125MHz

100MHz

Power

Organization

Interface

Package

Normal

4Banks x 2Mbits

x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-

scribed. No patent licenses are implied.

Rev. 1.3/Aug. 01

HY57V281620A

PIN CONFIGURATION

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

V

DD

LDQM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

V

SS

NC

UDQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

PIN DESCRIPTION

CLK

Clock

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

RAS, CAS and WE define the operation

Refer function truth table for details

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power supply for internal circuits and input buffers

Power supply for output buffers

No connection

CKE

CS

BA0, BA1

Clock Enable

Chip Select

Bank Address

A0 ~ A11

Address

Row Address Strobe, Col-

umn Address Strobe, Write

Enable

Data Input/Output Mask

Data Input/Output

Power Supply/Ground

Data Output Power/Ground

No Connection

RAS, CAS, WE

UDQM, LDQM

DQ0 ~ DQ15

V

DD

/V

SS

V

DDQ

/V

SSQ

NC

Rev. 1.3/Aug. 01

3

HY57V281620A

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh logic

& timer

Internal Row

counter

CLK

Row active

2Mx16 Bank 3

Row

Pre

Decoders

2Mx16 Bank 2

X decoders

2Mx16 Bank 1

2Mx16 Bank 0

X decoders

DQ0

DQ1

I/O Buffer & Logic

Sense AMP & I/O Gate

X decoders

CKE

CS

State Machine

RAS

CAS

WE

UDQM

LDQM

refresh

Column

Active

Memory

Cell

Array

Column

Pre

Decoders

Y decoders

DQ14

DQ15

Bank Select

Column Add

Counter

A0

A1

Address buffers

A11

BA0

BA1

Address

Registers

Burst

Counter

Mode Registers

CAS Latency

Data Out Control

Pipe Line Control

Rev. 1.3/Aug. 01

4

HY57V281620A

ABSOLUTE MAXIMUM RATINGS

Parameter

Ambient Temperature

Storage Temperature

Voltage on Any Pin relative to V

S S

Voltage on V

DD

relative to V

SS

Short Circuit Output Current

Power Dissipation

Soldering Temperature

⋅

Time

T

A

T

STG

V

IN

, V

OUT

V

DD,

V

DDQ

I

O S

P

D

T

SOLDER

Symbol

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

50

1

260

⋅

10

Rating

°C

V

mA

W

°C ⋅

Sec

Unit

Note :

Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION

(T

A

=0 to 70°C )

Parameter

Power Supply Voltage

Input High voltage

Input Low voltage

Symbol

V

DD

, V

DDQ

V

IH

V

IL

Min

3.0

2.0

-0.3

Typ

3.3

3.0

0

Max

3.6

V

DDQ

+ 0.3

0.8

Unit

V

Note

1

1,2

1,3

Note :

1.All voltages are referenced to V

SS

= 0V

2.V

IH

(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.V

IL

(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION

(T

A

=0 to 70°

C,

V

DD

=3.3

±

0.3V, V

SS

=0V)

Parameter

AC Input High / Low Level Voltage

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

Symbol

V

IH

/ V

IL

Vtrip

tR / tF

Voutref

C

L

Value

2.4/0.4

1.4

1

1.4

50

Unit

V

ns

V

pF

1

Note

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output

load circuit

Rev. 1.3/Aug. 01

5

HY57V281620A

CAPACITANCE

(TA=25°C, f=1MHz)

-6/7/K/H

Parameter

Symbol

Min

Input capacitance

CLK

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS ,

WE, UDQM, LDQM

Data input / output capacitance

DQ0 ~ DQ15

C

I1

CI

2

2.5

Max

3.5

3.8

Min

2.5

Max

4.0

5.0

pF

-8/P/S

Unit

C

I/O

4.0

6.5

4.0

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250

Ω

Output

50pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I

(TA=0 to 70°

C,

V

DD

=3.3

±

0.3V)

Parameter

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

I

LI

I

LO

V

OH

V

OL

Symbol

Min.

-1

2.4

-

Max

1

-

0.4

Unit

uA

V

Note

1

2

I

OH

= -4mA

I

OL

= +4mA

Note :

1.V

IN

= 0 to 3.6V, All other pins are not tested under V

IN

=0V

2.D

OUT

is disabled, V

OUT

=0 to 3.6

Rev. 1.3/Aug. 01

6

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