Integrated Synthesizer and VCO
ADF4360-0
FEATURES
Output frequency range: 2400 MHz to 2725 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
GENERAL DESCRIPTION
The ADF4360-0 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-0 is designed
for a center frequency of 2600 MHz. In addition, a divide-by-2
option is available, whereby the user gets an RF output of be-
tween 1200 MHz and 1360 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
DD
CE
R
SET
ADF4360-0
MULTIPLEXER
REF
IN
14-BIT R
COUNTER
LOCK
DETECT
CLK
DATA
LE
24-BIT
DATA REGISTER
24-BIT
FUNCTION
LATCH
PHASE
COMPARATOR
V
VCO
V
TUNE
C
C
C
N
MUTE
MUXOUT
CHARGE
PUMP
CP
INTEGER
REGISTER
VCO
CORE
OUTPUT
STAGE
RF
OUT
A
13-BIT B
COUNTER
PRESCALER
P/P+1
LOAD
LOAD
5-BIT A
COUNTER
RF
OUT
B
N = (BP + A)
MULTIPLEXER
DIVSEL = 1
÷2
DIVSEL = 2
AGND
DGND
CPGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
04644-0-001
ADF4360-0
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
PFD and Charge Pump................................................................ 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Register..................................................................... 10
VCO ............................................................................................. 10
Output Stage................................................................................ 11
Latch Structure ........................................................................... 12
Control Latch .............................................................................. 16
N Counter Latch......................................................................... 17
R Counter Latch ......................................................................... 17
Applications..................................................................................... 18
Fixed Frequency LO................................................................... 18
Power-Up..................................................................................... 18
Interfacing ................................................................................... 18
PCB Design Guidelines for Chip Scale Package........................... 19
Output Matching ........................................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADF4360-0
SPECIFICATIONS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
REF
IN
Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
2
CHARGE PUMP
I
CP
Sink/Source
3
High Value
Low Value
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
I
OH
, Output High Current
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
VCO
AI
DD4
DI
DD4
I
VCO4, 5
I
RFOUT4
Low Power Sleep Mode
4
RF OUTPUT CHARACTERISTICS
5
VCO Output Frequency
VCO Sensitivity
Lock Time
6
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power
5, 7
Output Power Variation
VCO Tuning Range
VCO Tuning Port Leakage Current
B Version
10/250
0.7/AV
DD
0 to AV
DD
5.0
±100
8
Unit
MHz min/max
V p-p min/max
V max
pF max
µA max
MHz max
With R
SET
= 4.7 kΩ.
2.5
0.312
2.7/10
0.2
2
1.5
2
1.5
0.6
±1
3.0
DV
DD
– 0.4
500
0.4
3.0/3.6
AV
DD
AV
DD
10
2.5
19.0
3.5 to 11.0
7
2400/2725
56
250
1
15
−30
−39
−13/−6.5
±3
1.25/2.50
0.2
mA typ
mA typ
kΩ
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
µA max
V max
V min/V max
CMOS output chosen.
I
OL
= 500 µA.
Conditions/Comments
For f < 10 MHz, use dc-coupled
CMOS compatible square wave, slew rate > 21 V/µs.
AC-coupled.
CMOS compatible.
1.25 V ≤ V
CP
≤ 2.5 V.
1.25 V ≤ V
CP
≤ 2.5 V.
V
CP
= 2.0 V.
mA typ
mA typ
mA typ
mA typ
µA typ
MHz min/max
MHz/V typ
µs typ
MHz/V typ
kHz typ
dBc typ
dBc typ
dBm typ
dB typ
V min/max
nA typ
I
CORE
= 10 mA.
RF output stage is programmable.
I
CORE
= 15 mA.
To within 10 Hz of final frequency.
Into 2.00 VSWR load.
Programmable in 3 dB steps. See Table 7.
For tuned loads, see Output Matching section.
Rev. 0 | Page 3 of 20
ADF4360-0
Parameter
NOISE CHARACTERISTICS
5
VCO Phase Noise Performance
8
B Version
−111
−133
−140
−145
−172
−163
−147
−80
1.4
−75
−45
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
dBm typ
Conditions/Comments
@ 100 kHz offset from carrier.
@ 1 MHz offset from carrier.
@ 3 MHz offset from carrier.
@ 10 MHz offset from carrier.
@ 25 kHz PFD frequency.
@ 200 kHz PFD frequency.
@ 8 MHz PFD frequency.
@ 1 kHz offset from carrier.
100 Hz to 100 kHz.
Synthesizer Phase Noise Floor
9
In-Band Phase Noise
10, 11
RMS Integrated Phase Error
12
Spurious Signals due to PFD Frequency
11, 13
Level of Unlocked Signal with MTLD Enabled
1
2
Operating temperature range is: –40°C to +85°C.
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant loop gain over the frequency range.
4
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V; P = 32.
5
These characteristics are guaranteed for VCO core power = 10 mA.
6
Jumping from 2.4 GHz to 2.725 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
Using 50 Ω resistors to V
VCO
, into a 50 Ω load. For tuned loads, see Output Matching.
8
The noise of the VCO is measured in open-loop conditions.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log
N
(where
N
is the N divider value).
10
The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; N = 2600; Loop B/W = 10 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 2600; Loop B/W = 25 kHz.
13
The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; f
REFOUT
= 10 MHz @ 0 dBm.
Rev. 0 | Page 4 of 20
ADF4360-0
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE Setup Time
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
t
4
CLOCK
t
5
t
2
DATA
DB23 (MSB)
DB22
t
3
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
LE
t
1
LE
t
6
04414-0-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 20
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