72801L10TF8 datasheet, PDF - EEWORLD Datasheet

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72801L10TF8: DescriptionTQFP-64, Reel; Categorystorage; File Size259KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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72801L10TF8 Overview

TQFP-64, Reel

72801L10TF8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	SLIM, TQFP-64
Contacts	64
Manufacturer packaging code	PP64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
Maximum access time	6.5 ns
Maximum clock frequency (fCLK)	100 MHz
period time	10 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
memory density	2304 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	2
Number of terminals	64
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256X9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
Base Number Matches	1

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DUAL CMOS SyncFIFO™

DUAL 256 x 9, DUAL 512 x 9,

DUAL 1,024 x 9, DUAL 2,048 x 9,

DUAL 4,096 x 9, DUAL 8,192 x 9

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

IDT72801

IDT72811

IDT72821

IDT72831

IDT72841

IDT72851

FEATURES:

•

The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs

The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs

The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs

The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs

The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs

The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs

Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

Ideal for prioritization, bidirectional, and width expansion

applications

10 ns read/write cycle time for the IDT72801/72811/72821/72831/

72841/72851

Separate control lines and data lines for each FIFO

Separate Empty, Full, Programmable Almost-Empty and Almost-

Full flags for each FIFO

Enable puts output data lines in high-impedance state

Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin

Quad Flatpack (STQFP)

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

The IDT72801/72811/72821/72831/72841/72851 are dual synchronous

(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/

72221/72231/72241/72251 FIFOs in a single package with all associated

control, data, and flag lines assigned to separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0

- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each

input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write

Enable pins (WENA1, WENA2,

WENB1,

WENB2). Data is written into each of

the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)

when the appropriate write enable pins are asserted.

The output port of each FIFO bank is controlled by its associated clock pin

(RCLKA, RCLKB) and two Read Enable pins (RENA1,

RENA2, RENB1,

RENB2).

The Read Clock can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual clock operation.

An Output Enable pin (OEA,

OEB)

is provided on the read port of each FIFO

for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (EFA,

EFB)

and Full (FFA,

FFB).

Two programmable flags, Almost-Empty (PAEA,

PAEB)

and Almost-Full

(PAFA,

PAFB),

are provided for each FIFO bank to improve memory utilization.

If not programmed, the programmable flags default to empty+7 for

PAEA

and

PAEB,

and full-7 for

PAFA

and

PAFB.

The IDT72801/72811/72821/72831/72841/72851 architecture lends itself

to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

These FIFOs is fabricated using high-performance submicron CMOS

technology.

FUNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

DA0 - DA8

EFA

PAEA

PAFA

LDA

FFA

WCLKB

WENB1

WENB2

DB0 - DB8

LDB

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

INPUT REGISTER

OFFSET REGISTER

EFB

PAEB

PAFB

FFB

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

OUTPUT REGISTER

RSA

OEA

QA0 - QA8

RCLKA

RENA1

RENA2

RSB

OEB

QB0 - QB8

RCLKB

RENB1

RENB2

3034 drw 01

IDT, IDT logo and the

SyncFIFO

logo are registered trademarks of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

FEBRUARY 2018

DSC-3034/7

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