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IDT70V08L

Description
64K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
Categorystorage   
File Size165KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT70V08L Overview

64K X 8 DUAL-PORT SRAM, 20 ns, PQFP100

IDT70V08L Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals100
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
maximum access time20 ns
Processing package description14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeFLATPACK, LOW PROFILE, FINE PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.5000 mm
terminal coatingTIN LEAD
Terminal locationQUAD
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
memory width8
organize64K X 8
storage density524288 deg
operating modeASYNCHRONOUS
Number of digits65536 words
Number of digits64K
Memory IC typeDUAL-PORT SRAM
serial parallelPARALLEL
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35ns (max.)
Low-power operation
– IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V08 easily expands data bus width to 16 bits or
x
IDT70V08S/L
x
x
x
x
x
x
x
x
x
x
x
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
x
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
BUSY
R
64Kx8
MEMORY
ARRAY
70V08
A
15R
A
0R
A
15L
A
0L
Address
Decoder
Address
Decoder
A
15L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
M/S
NOTES:
1.
BUSY
is an input as a Slave (M/S-V
IL
) and an output when it is a Master (M/S-V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
15R
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3740 drw 01
(1)
JANUARY 2001
DSC-3740/4
1
©2000 Integrated Device Technology, Inc.
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